Texas Instruments Corporation

Richard A Chapman

Mark Stephen Rodder

Roger A Haken

Michael A Kinch

Theodore Warren Houston

Jaroslav Hynecek

Amitava Chatterjee

Che-Chia Wei

Clarence W Teng

Keith Alan Joyner

Dennis D Buss

Thomas E Tang

Syed Suhail Murtaza

Howard L Tigelaar

Thomas C Holloway

William G Manns

Kenneth E Bean

Bert R Riemenschneider

Andrew T Appel

Adam J Lewis, Jr

Milo R Johnson

Henry B Morris

Raymond J Jasinski

Suhail Murtaza

A method of fabricating a CMOS transistor to construct shallow drain extenders ( ) using a replacement gate design. The method involves forming epitaxial layers ( ) and ( ) the will later function as shallow drain extensions. The etching of the replacement gate ( ) and the formation of inner sidewalls ( ) serve to define the transistor gate length.

Shallow drain extenders for CMOS transistors using replacement gate design

A semiconductor device having high and low voltage transistors on the same chip. High voltage NMOS transistor comprises a polysilicon gate doped at first dopant level. Low voltage NMOS transistor comprises a polysilicon gate doped at a second dopant level. The second dopant level is higher than the first. High voltage PMOS transistor comprises a polysilicon gate doped at a third dopant level. Low voltage PMOS transistor comprises a polysilicon gate doped at a fourth dopant level. The fourth dopant level is higher than the third.

Using a change in doping of poly gate to permit placing both high voltage and low voltage transistors on the same chip

A transistor (,) having a strip channel or channels (,) in which the current flow in is the lateral direction between source (,) and drain (,). The gate (,) is located on the sidewalls and, if desired, the top of the strip channel (,). In a preferred embodiment of the invention, a disposable gate process is used that allows the source (,) and drain (,) regions to be self-aligned to the gate (,).

Self-aligned trenched-channel lateral-current-flow transistor

A counter-doped epitaxial silicon (doped opposite to the substrate type) is used to form the buried layer in a CMOS transistor, while maintaining an abrupt channel profile. Shallow source/drain junctions with abrupt source/drain profiles may be formed using raised (or elevated) source/drain design. The invention encompasses a transistor structure including a doped silicon substrate, and an oppositely-doped epitaxial silicon layer formed on the substrate. A gate is formed on the epitaxial layer, the gate defining a channel region in the epitaxial layer underneath the gate. A layer is formed on the epitaxial silicon layer on opposing sides of, and is electrically isolated from, the gate.

Disposable gate/replacement gate MOSFETs for sub-0.1 micron gate length and ultra-shallow junctions

Disposable gate/replacement gate MOSFETS for sub-0.1 micron gate length

A transistor (100) having a strip channel or channels (108) in which the current flow in is the lateral direction between source (110) and drain (112). The gate (116) is located on the sidewalls and, if desired, the top of the strip channel (108). In a preferred embodiment of the invention, a disposable gate process is used that allows the source (110) and drain (112) regions to be self-aligned to the gate (116).

A method for forming a MOSFET transistor (100) using a disposable gate (120). A disposable gate (120) having at least two materials (122,124) that may be etched selectively with respect to each other is formed on a semiconductor substrate (102). Source/drain regions (104) are then formed adjacent the disposable gate. The source/drain regions may, for example, include raised source/drain regions (106). An insulator layer (114) is then deposited over the structure and then a portion of the insulator layer (114) over the disposable gate (120) is removed (e.g., using CMP or an etch-back). The composition of the insulator layer (114) is chosen such that the top layer (124) of the disposable gate (120) may be removed selectively with respect to the insulator layer (114). The disposable gate (120) is then removed and a channel implant may be performed that is self-aligned and only in the channel region. The gate dielectric (110) and gate electrode (112) are then formed.

Method of forming a MOSFET using a disposable gate and raised source and

A process for forming high voltage and low voltage transistors on the same substrates includes first forming a poly gate (16) over layer gate oxide (10) on a substrate (12). An LDD implant is then performed, followed by the formation of a nitride cap (30) over the gate (16). The cap (30) is not disposed over gate electrodes associated with low voltage transistors. Thereafter, the source/drain implant is performed which forms source/drain regions (40) and (42). The cap (30) prevents the introduction of dopants into the gate electrode (16) during the source/drain implant step. This effectively increases the gate oxide width due to a larger depletion region at the oxide/polysilicon gate boundary as compared to the low voltage transistors with the higher dopant levels and the gate electrode.

Method for forming high voltage and low voltage transistors on the same

An isotropic or partially isotropic etch shrinks lithographically patterned photoresist (211, 212) to yield reduced linewidth patterned photoresist (213, 214) with a buried antireflective coating also acting as an etchstop or a sacrificial layer. The reduced linewidth pattern (213, 214) provide an etch mask for subsequent anisotropic etching of underlying material such as polysilicon (206) or metal or insulator or ferroelectric.

Intermediate layer lithography

A method is provided for increasing the electrical activation of dopants in a semiconductor device using rapid thermal processing (RTP). An aspect of the invention includes forming a gate on a semiconductor body (12), such as a substrate (14), and implanting a dopant (28) into the semiconductor body (12) proximate the gate. The dopant (28) is partially activated using a furnace. The dopant (28) is further activated using RTP. The activation of the dopant (28) through RTP in addition to the furnace annealing allows almost complete activation of the dopant while maintaining acceptable channel depths.

RTP booster to semiconductor device anneal

One embodiment of the present invention is a method of simultaneously forming high-voltage (12) and low-voltage (10) devices on a single substrate (14), the method comprising: forming a thin oxide layer (18) on the substrate, the thin oxide layer having a desired thickness for a gate oxide for the low-voltage device; selectively forming a gate structure (30) for the high-voltage device, the thin oxide is situated between the gate structure and the substrate; and selectively thickening the thin oxide under the gate structure while keeping the thin oxide layer utilized for the low-voltage device at the desired thickness.

Process for thickening selective gate oxide regions

A semiconductor device having high and low voltage transistors on the same chip. High voltage NMOS transistor 76 comprises a polysilicon gate 40 doped at a first dopant level. Low voltage NMOS transistor comprises a polysilicon gate 44 doped at a second dopant level. The second dopant level is higher than the first. High voltage PMOS transistor 84 comprises a polysilicon gate 48 doped at a third dopant level. Low voltage PMOS transistor comprises a polysilicon gate 52 doped at a fourth dopant level. The fourth dopant level is higher than the third.

Using a change in doping of poly gate to permit placing both high

A process for forming N-channel MOS sources and drains, by implanting both phosphorus and arsenic. The high diffusivity of phosphorus causes it to diffuse in advance of the bulk of the arsenic, so that, after annealing, the source/drain regions have graded regions of gradually decreasing conductivity adjacent to the end of the channels. Thus the electric potential gradient at the ends of the channels is reduced, and impact ionization and hot carrier effects are avoided. The effective radius of the source (or drain) junction is increased, providing increased breakdown voltage. The implantation of both phosphorus and arsenic with the resultant phosphorus peripheral band after annealing is used with self-aligned silicided source/drain regions to prevent silicide spiking through shallow arsenic regions to the P substrate and to prevent source/drain junction consumption during silicidation.

Silicided MOS transistor

The disclosure relates to a MOSFET-protected nonvolatile capacitor cell which has a storage gate and a nonvolatile stack thereunder, the cell having a heavily doped n+ ring surrounding the storage gate and an n-type tank disposed beneath the stack and electrically connected to the n+ type ring.

Nonvolatile capacitor random access memory

The invention is an improved layout for integrated circuits employing local interconnect pads, particularly six-transistor SRAM circuits, comprising a local interconnect pad which electrically bridges two segments of a conducting line and an active device, and a method for employing the layout.

Growing community of inventors

Dallas, TX, United States of America

Richard A Chapman