Siliconix Incorporated

Stmicroelectronics Gmbh

Sgs-thomson Microelectronics Limited

Other

United States of America As Represented by the Administrator of Nasa

Fairchild Semiconductor Corporation

National Semiconductor Corporation

Tyco Electronics Corporation

Sgs-thomson Microelectronics S.r.l.

Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno

Vlsi Technology, Inc.

Infineon Technologies North America Corp.

Ixys Corporation

Stmicroelectronics N.v.

Bourns Incorporated

Richard A Blanchard

William C Alexander

Jun Zeng

Mohamed N Darwish

William Johnstone Ray

Mark David Lowenthal

Vladimir Rodov

Hidenori Akiyama

Woytek Tworzydlo

Neil O Shotton

Adrian I Cogan

Mark Allan Lewandowski

Brad Oraw

Donald Odell Frazier

Kirk A Fuller

Jeffrey Baldridge

Jean-Michel Guillot

Richard Kent Williams

Paul McKay Moore

Eric Anthony Perozziello

Fwu-Iuan Hshieh

Steven B Roach

Eric Kahrs

Darin Wagner

Larry Todd Biggs

Ferruccio Frisina

Giuseppe Ferla

Michael LeFebvre

Chye Kiat Ang

Hamza Yilmaz

Theodore I Kamins

Tsiu Chiu Chan

Constantin Bulucea

Koon Chong So

James A Cunningham

Yu-Pin Han

Xiaorong Cai

Angelo Magri

Elmer H Guritz

Shih-Tzung Su

Robert Kuo-Chang Yang

Robert W Busse

Muhammed Ayman Shibib

Jin Qiu

Barry Lee Chin

Raffaele Zambrano

Nathan Zommer

Pierangelo Confalonieri

Scott A Kreps

David L Whitney

Joseph Colby McAlexander, Iii

Angelo Magri'

Gary Michael Hurtz

Alexei Ankoudinov

Kalipatnam Vivek Rao

Lorimer K Hill

Alireza Mojab

Kui Pu

Benedict C Choy

Alexander Ray

William P Imhauser

David Cooper

David H Soo

Robert O Groover

Wenfang Du

Henry C Pao

James D Plummer

Michael J Callahan

Bradley Whaley

Shelby Jueden

Woytek Tworzydio

Françoise Hébert

Richard K Robinson

Trenches having a gate oxide layer are formed in the surface of a silicon wafer for vertical gates. Conductive doped polysilicon is then deposited in the trenches to form a relatively thin layer of doped polysilicon along the sidewalls. Thus, there is a central cavity surrounded by polysilicon. Next, the cavity is filled in with a much higher conductivity material, such as aluminum, copper, a metal silicide, or other conductor to greatly reduce the overall resistivity of the trenched gates. The thin polysilicon forms an excellent barrier to protect the gate oxide from diffusion from the inner conductor atoms. The inner conductor and the polysilicon conduct the gate voltage in parallel to lower the resistance of the gates, which increases the switching speed of the device. In another embodiment, a metal silicide is used as the first layer, and a metal fills the cavity.

Insulated trench gates with multiple layers for improved performance of semiconductor devices

The present application teaches, among other innovations, power semiconductor devices in which breakdown initiation regions, on BOTH sides of a die, are located inside the emitter/collector regions, but laterally spaced away from insulated trenches which surround the emitter/collector regions. Preferably this is part of a symmetrically-bidirectional power device of the 'B-TRAN' type. In one advantageous group of embodiments (but not all), the breakdown initiation regions are defined by dopant introduction through the bottom of trench portions which lie within the emitter/collector region. In one group of embodiments (but not all), these can advantageously be separated trench portions which are not continuous with the trench(es) surrounding the emitter/collector region(s).

Ruggedized symmetrically bidirectional bipolar power transistor

A sacrificial substrate wafer is provided. A low resistivity etch stop layer is formed on or in the top surface of the wafer. The etch stop layer may be a highly doped, p+ type epitaxially grown layer, or an implanted p+ type boron layer, or an epitaxially grown p+ type SiGe layer. Various epitaxial layers, such as an n− type drift layer, and doped regions are then formed over the etch stop layer to form a vertical power device. The starting wafer is then removed by a combination of mechanical grinding/polishing to leave a thinner layer of the starting wafer. A chemical or plasma etch is then used to remove the remainder of the starting wafer, using the etch stop layer to automatically stop the etching. A bottom metal electrode is then formed on the etch stop layer. The etch stop layer injects hole carriers into the drift layer.

Etch stop layer for injecting carriers into drift layer for a vertical power device

Methods and systems for power semiconductor devices integrating multiple quasi-vertical transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

Lateral transistors and methods with low-voltage-drop shunt to body diode

In an insulated trench gate device, polysilicon in the trench is etched below the top surface of the trench, leaving a thin gate oxide layer exposed near the top of the trench. An angled implant is conducted that implants dopants through the exposed gate oxide and into the side of the trench. If the implanted dopants are n-type, this technique may be used to extend an n+ source region to be below the top of the polysilicon in the trench. If the implanted dopants are p&#x2212;type, the dopants may be used to form a p-MOS device that turns on when the polysilicon is biased with a negative voltage. P-MOS and n-MOS devices can be formed in a single cell using this technique, where turning on the n-MOS device turns on a vertical power switch, and turning on the p-MOS device turns off the power switch.

Insulated trench gates with dopants implanted through gate oxide

Layout to reduce current crowding at endpoints. At least one example is a semiconductor device comprising: an emitter region defining an inner boundary in the shape of an obround with parallel sides, and the obround having hemispherical ends each having a radius; a base region having a first end, a second end opposite the first end, and base length, the base region disposed within the obround with the base length parallel to and centered between the parallel sides, the first end spaced apart from the first hemispherical end by a first gap greater than the radius, and the second end spaced apart from the second hemispherical ends by a second gap greater than the radius.

Layout to reduce current crowding at endpoints

After the various regions of a vertical power device are formed in or on the top surface of an n-type wafer, the wafer is thinned, such as by grinding. A drift layer may be n-type, and various n-type regions and p-type regions in the top surface contact a top metal electrode. A blanket dopant implant through the bottom surface of the thinned wafer is performed to form an n&#x2212; buffer layer and a bottom p+ emitter layer. Energetic particles are injected through the bottom surface to intentionally damage the crystalline structure. A wet etch is performed, which etches the damaged crystal at a much greater rate, so some areas of the n&#x2212; buffer layer are exposed. The bottom surface is metallized. The areas where the metal contacts the n&#x2212; buffer layer form cathodes of an anti-parallel diode for conducting reverse voltages, such as voltage spikes from inductive loads.

Anti-parallel diode formed using damaged crystal structure in a vertical power device

Methods and systems for double-sided semiconductor device fabrication. Devices having multiple leads on each surface can be fabricated using a high-temperature-resistant handle wafer and a medium-temperature-resistant handle wafer. Dopants can be introduced on both sides shortly before a single long high-temperature diffusion step diffuses all dopants to approximately equal depths on both sides. All high-temperature processing occurs with no handle wafer or with a high-temperature handle wafer attached. Once a medium-temperature handle wafer is attached, no high-temperature processing steps occur. High temperatures can be considered to be those which can result in damage to the device in the presence of aluminum-based metallizations.

Systems and methods for bidirectional device fabrication

A design technique is disclosed that divides up a cellular power switch into different size segments. Each segment is driven by a different driver circuit. The selection of the combination of segments is made to minimize the combined conduction and switching losses of the power switch. For example, for very light loads, switching losses dominate so only a small segment is activated for driving the load. For medium and high load currents, conduction losses become more significant, so additional segments are activated to minimize the total losses. In one embodiment, the number of cells in the segments is binary weighted, such as 1&#xd7;, 2&#xd7;, and 4&#xd7;, so that there are seven different combinations of segments. The drivers may be configured to achieve the same or different slew rates of the segments, such as to reduce transients. The segments may all be in the same die or a plurality of dies.

Insulated gate power device with independently controlled segments

An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n&#x2212; epi layer, a p-well, trenched insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device may be formed of a matrix of cells or may be interdigitated. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for rapidly turning the device off. The p-channel MOSFET may be made a depletion mode device by implanting boron ions at an angle into the trenches to create a p-channel. This allows the IGTO device to be turned off with a zero gate voltage while in a latch-up condition, when the device is acting like a thyristor.

Cell layouts for MOS-gated devices for improved forward voltage

A vertical transistor structure in which a recessed field plate trench surrounds multiple adjacent gate electrodes. Thus the specific on-state conductance is increased, since the ratio of recessed field plate area to channel area is reduced. Various versions use two, three, or more distinct gate electrodes within the interior of a single RFP or RSFP trench's layout.

High density power device with selectively shielded recessed field plate

Over a flexible substrate are deposited stacked pixel layers including a bottom layer of LEDs forming blue pixels, a middle layer of LEDs forming green pixels, and a top layer of LEDs forming red pixels. Each LED die comprises an LED portion and an integrated transistor portion. Applying a voltage to a control terminal of the transistor portion energizes the LED portion. The pixels are substantially transparent, due to the LEDs being microscopic and the pixel areas being much larger, to allow light from the underlying layers to pass through. The three layers of pixels are aligned so that a combination of a single top red pixel, a single underlying green pixel, and a single underlying blue pixel form a single multi-color pixel. The different layers have transparent column and row lines.

Three-layer color display using stacked LED layers

Three-layer color display using active LED dies

A high power vertical insulated-gate switch is described that includes a parallel cell array having inner cells and an edge cell. The cells have a vertical npnp structure with a trenched field effect device that turns the device on and off. The edge cell is prone to breaking down at high currents. Techniques used to cause the current in the edge cell to be lower than the current in the inner cells, to improve robustness, include: forming a top n-type source region to not extend completely across opposing trenches in areas of the edge cell; forming the edge cell to have a threshold voltage of its field effect device that is greater than the threshold voltage of the field effect devices in the inner cells; and providing a resistive layer between the edge cell and a top cathode electrode electrically contacting the inner cells and the edge cell.

Cellular insulated gate power device with edge design to prevent failure near edge

Growing community of inventors

Los Altos, CA, United States of America

Richard A Blanchard