International Business Machines Corporation

Interuniversitair Microelektronica Centrum (imec)

Imec Vzw

Ricardo Alves Donaton

Dureseti Chidambarrao

William K Henson

Kern Rim

Michael Patrick Chudzik

Herbert Lei Ho

Babar Ali Khan

Xinhui Wang

Rishikesh Krishnan

Nicolas L Breil

Deepal Wehella-Gamage

Dong Hun Kang

Sampath Purushothaman

Matthew Earl Colburn

Kevin Shawn Petrarca

Xiao Hu Liu

Conal Eugene Murray

Satyanarayana Venkata Nitta

Shahab Siddiqui

Naim Moumen

Yue Liang

Karen Irma Maex

Mikhail Rodionovich Baklanov

Sujatha Sankaran

Rita Rooyackers

Karl W Barth

Ludo Deferm

Spyridon Galis

Philippe Jansen

Rita Verbeeck

Jack Allan Mandelman

Theodorus E Standaert

Stephen McConnell Gates

Wai-Kin Li

Shreesh Narasimha

Richard Stephan Wise

Ravikumar Ramachandran

Wu-Song S Huang

Renee Tong Mo

Huiming Bu

Jason Scott Orcutt

Siddarth A Krishnan

Wesley Charles Natzle

Kuang-Jung Chen

Hongwen Yan

Abram L Falk

Xi Li

Anda C Mocuta

Yaocheng Liu

Serge Vanhaelemeersch

Rashmi Jha

David M Onsongo

Chi Xiong

Swetha Kamlapurkar

Marc Schaekers

Amanda L Tessier

Herbert Struyf

Thedorus Eduardos Standaert

Liu Yaocheng

Paul Chung-Muh Chang

Michael Baklanov

Karen Irma Josef Maex

Techniques regarding microwave-to-optical quantum transducers are provided. For example, one or more embodiments described herein can include an apparatus that can include a microwave resonator on a dielectric substrate and adjacent to an optical resonator, and a photon barrier structure at least partially surrounding an optical resonator, wherein the photon barrier structure is configured to provide isolation of the microwave resonator from optical photons in the dielectric substrate outside the photon barrier structure.

Microwave-to-optical quantum transducers

An integrated FinFET and deep trench capacitor structure and methods of manufacture are provided. The method includes forming deep trench capacitor structures in a silicon on insulator (SOI) wafer. The method further includes forming a plurality of composite fin structures from a semiconductor material of the SOI wafer and conductive material of the deep trench capacitor structures. The method further includes forming a liner over the deep trench capacitor structures including the conductive material of the deep trench capacitor structures. The method further includes forming replacement gate structures with the liner over the deep trench capacitor structures protecting the conductive material during deposition and etching processes.

Semiconductor structures with deep trench capacitor and methods of manufacture

Method of forming a deep trench capacitor are provided. The method may include forming a deep trench in a substrate; forming a metal-insulator-metal (MIM) stack within a portion of the deep trench, the MIM stack forming including forming an outer electrode by co-depositing a refractory metal and silicon into the deep trench; and filling a remaining portion of the deep trench with a semiconductor.

DT capacitor with silicide outer electrode and/or compressive stress layer, and related methods

A deep trench capacitor is provided. The deep trench capacitor may include: a deep trench in a substrate, the deep trench including an lower portion having a width that is wider than a width of the rest of the deep trench; a compressive stress layer against the substrate in the lower portion; a metal-insulator-metal (MIM) stack over the compressive stress layer, the MIM stack including a node dielectric between an inner electrode and an outer electrode; and a semiconductor core within the MIM stack.

Method of forming a deep trench capacitor are provided. The method may include forming a deep trench in a substrate; enlarging a width of a lower portion of the deep trench to be wider than a width of the rest of the deep trench; epitaxially forming a compressive stress layer in the lower portion of the deep trench; forming a metal-insulator-metal (MIM) stack within the lower portion of the deep trench; and filling a remaining portion of the deep trench with a semiconductor. Alternatively to forming the compressive stress layer or in addition thereto, a silicide may be formed by co-deposition of a refractory metal and silicon.

Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions.

Hybrid bonding interface for 3-dimensional chip integration

A method and structure to scale metal gate height in high-k/metal gate transistors. A method includes forming a dummy gate and at least one polysilicon feature, all of which are formed from a same polysilicon layer and wherein the dummy gate is formed over a gate metal layer associated with a transistor. The method also includes selectively removing the dummy gate while protecting the at least one polysilicon feature. The method further includes forming a gate contact on the gate metal layer to thereby form a metal gate having a height that is less than half a height of the at least one polysilicon feature.

Method and structure for gate height scaling with high-k/metal gate technology

The present invention provides a method of forming a threshold voltage adjusted gate stack in which an external acid diffusion process is employed for selectively removing a portion of a threshold voltage adjusting layer from one device region of a semiconductor substrate. The external acid diffusion process utilizes an acid polymer which when baked exhibits an increase in acid concentration which can diffuse into an underlying exposed portion of a threshold voltage adjusting layer. The diffused acid reacts with the exposed portion of the threshold voltage adjusting layer providing an acid reacted layer that can be selectively removed as compared to a laterally adjacent portion of the threshold voltage adjusting layer that is not exposed to the diffused acid.

Method for removing threshold voltage adjusting layer with external acid diffusion process

An electronic structure including a substrate having a having a dielectric layer with at least one metallic interconnect structure within and a dielectric barrier layer above the dielectric layer, and a multi-layer hardmask stack coated with a self-assembled layer, where the self-assembled layer is a pattern of nanoscale and/or microscale voids which are generated into the dielectric barrier layer and into the dielectric layer next to the metallic interconnect structure to create columns in the dielectric barrier layer and dielectric layer therein. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like.

Electronics structures using a sacrificial multi-layer hardmask scheme

A CMOS structure includes an n-FET device comprising an n-FET channel region and a p-FET device comprising a p-FET channel region. The n-FET channel region includes a first silicon material layer located upon a silicon-germanium alloy material layer. The p-FET channel includes a second silicon material layer located upon a silicon-germanium-carbon alloy material layer. The silicon-germanium alloy material layer induces a desirable tensile strain within the n-FET channel. The silicon-germanium-carbon alloy material layer suppresses an undesirable tensile strain within the p-FET channel region. A silicon-germanium-carbon alloy material from which is comprised the silicon-germanium-carbon alloy material layer may be formed by selectively incorporating carbon into a silicon-germanium alloy material from which is formed the silicon-germanium alloy material layer.

CMOS structure including differential channel stressing layer compositions

A low resistance contact is formed to a metal gate or a transistor including a High-&#x3ba; gate dielectric in a high integration density integrated circuit by applying a liner over a gate stack, applying a fill material between the gate stacks, planarizing the fill material to support high-resolution lithography, etching the fill material and the liner selectively to each other to form vias and filling the vias with a metal, metal alloy or conductive metal compound such as titanium nitride.

Direct contact between high-&#x3ba;/metal gate and wiring process flow

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Cortlandt Manor, NY, United States of America

Ricardo Alves Donaton