Intel Corporation

Applied Materials, Inc.

Lam Research Corporation

Tohoku University

Mie Fujitsu Semiconductor Limited

Suvolta, Inc.

Reza Arghavani

Robert S Chau

Samantha SiamHwa Tan

Li-Qun Xia

Been-Yih Jin

Jack T Kavalieros

Mark L Doczy

Shankar Venkataraman

Zheng Yuan

Derek R Witty

Ellie Y Yieh

Adrien Lavoie

Lucian Shifren

Hichem M'Saad

Mihaela A Balseanu

Shankar Swaminathan

Scott E Thompson

Bhadri N Varadarajan

Pushkar Ranade

Amir Hamed Al-Bayati

Jun Qian

Vladimir Zubkov

Bruce E Beattie

Atif Noori

Simon Yang

Ananda K Banerji

John Graham

Catherine De Villeneuve

Junichi Koike

Yang Pan

Peter K Moon

Brian E Roberds

Daniel Peter

Douglas W Barlage

Payman Aminzadeh

Robert S McFadden

Doug Barlage

Matthew V Metz

Nitin K Ingle

Eric A Hudson

Michal Danek

Jeffrey S Marks

Alexandros T Demos

Scott A Hareland

Xinliang Lu

Yunsang Kim

Girish Anant Dixit

Chien-Teh Kao

Zhenjiang Cui

Kang Sub Yim

Nick Lindert

Sanjay Gopinath

Ishtak Karim

Timothy E Glassman

Gerardo Delgadino

Steven J Keating

Shashank C Deshmukh

Tom A Kamp

Michael C Kwan

Helen R Armer

Shruti Vivek Thombare

Benjamin A Bonner

Matthew Spuller

Weimin Han

Josephine J Chang

Meiyee (Maggie Le) Shek

Christopher G Parker

Lawrence Foley

Ken MacWilliams

Binny Arcot

Ron Dalesky

Bob McFadden

Melody Agustin

A semiconductor device includes a substrate, a conductive wiring which comprises cobalt or copper and is electrically connected to the substrate, an insulating material which electrically isolates the conductive wiring from neighboring wiring, and a first barrier layer which comprises a first cobalt alloy and is disposed between the conductive wiring and the insulating material.

Semiconductor devices including cobalt alloys and fabrication methods thereof

Disclosed herein are methods of doping a fin-shaped channel region of a partially fabricated 3-D transistor on a semiconductor substrate. The methods may include forming a multi-layer dopant-containing film on the substrate, forming a capping film comprising a silicon carbide material, a silicon nitride material, a silicon carbonitride material, or a combination thereof, the capping film located such that the multi-layer dopant-containing film is located in between the substrate and the capping film, and driving dopant from the dopant-containing film into the fin-shaped channel region. Multiple dopant-containing layers of the film may be formed by an atomic layer deposition process which includes adsorbing a dopant-containing film precursor such that it forms an adsorption-limited layer on the substrate and reacting adsorbed dopant-containing film precursor. Also disclosed herein are multi-station substrate processing apparatuses for doping the fin-shaped channel regions of partially fabricated 3-D transistors.

Capped ALD films for doping fin-shaped channel regions of 3-D IC transistors

Semiconductor devices including a first cobalt alloy in a first barrier layer and a second cobalt alloy in a second barrier layer

A method for patterning a substrate including multiple layers using a sulfur-based mask includes providing a substrate including a first layer and a second layer arranged on the first layer. The first layer includes a material selected from a group consisting of germanium, silicon germanium and type III/V materials. The method includes depositing a mask layer including sulfur species on sidewalls of the first layer and the second layer by exposing the substrate to a first wet chemistry. The method includes removing the mask layer on the sidewalls of the second layer while not completely removing the mask layer on the sidewalls of the first layer by exposing the substrate to a second wet chemistry. The method includes selectively etching the second layer relative to the first layer and the mask layer on the sidewalls of the first layer by exposing the substrate to a third wet chemistry.

Selective self-aligned patterning of silicon germanium, germanium and type III/V materials using a sulfur-containing mask

Disclosed herein are methods of doping a fin-shaped channel region of a partially fabricated 3-D transistor on a semiconductor substrate. The methods may include forming a multi-layer dopant-containing film on the substrate, forming a capping film comprising a silicon carbide material, a silicon carbonitride material, silicon oxycarbide material, silicon carbon-oxynitride, or a combination thereof, the capping film located such that the multi-layer dopant-containing film is located in between the substrate and the capping film, and driving dopant from the dopant-containing film into the fin-shaped channel region. Multiple dopant-containing layers of the film may be formed by an atomic layer deposition process which includes adsorbing a dopant-containing film precursor such that it forms an adsorption-limited layer on the substrate and reacting adsorbed dopant-containing film precursor. Also disclosed herein are multi-station substrate processing apparatuses for doping the fin-shaped channel regions of partially fabricated 3-D transistors.

Methods of doping semiconductor substrates using deposition of a rare earth metal-containing film such as an yttrium-containing film, and annealing techniques are provided herein. Rare earth metal-containing films are deposited using gas, liquid, or solid precursors without a bias and may be deposited conformally. Some embodiments may involve deposition using a plasma. Substrates may be annealed at temperatures less than about 500&#xb0; C.

Rare earth metal surface-activated plasma doping on semiconductor substrates

A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced &#x3c3;V(variation in V) compared to conventional bulk CMOS and can allow the threshold voltage Vof FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the Vsetting within a precise range. This Vset range may be extended by appropriate selection of metals of a gate electrode material so that a very wide range of Vsettings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control V(with a low &#x3c3;V) and V(the operating voltage supplied to the transistor), so that the body bias can be tuned separately from Vfor a given device.

Transistor with threshold voltage set notch and method of fabrication thereof

Methods of depositing and tuning deposition of sub-stoichiometric titanium oxide are provided. Methods involve depositing highly pure and conformal titanium on a substrate in a chamber by (i) exposing the substrate to titanium tetraiodide, (ii) purging the chamber, (iii) exposing the substrate to a plasma, (iv) purging the chamber, (v) repeating (i) through (iv), and treating the deposited titanium on the substrate to form sub-stoichiometric titanium oxide. Titanium oxide may also be deposited prior to depositing titanium on the substrate. Treatments include substrate exposure to an oxygen source and/or annealing the substrate.

[object Object]

A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced &#x3c3;Vcompared to conventional bulk CMOS and can allow the threshold voltage Vof FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the Vsetting within a precise range. This Vset range may be extended by appropriate selection of metals so that a very wide range of Vsettings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control V(with a low &#x3c3;V) and V, so that the body bias can be tuned separately from Vfor a given device.

The embodiments herein relate to methods and apparatus for etching a recessed feature in dielectric material. In various embodiments, a recessed feature is formed in two etching operations. The first etching operation partially etches the features and may take place in a reactor configured to produce a capacitively coupled plasma. The first etching operation may end before the underlying semiconductor material experiences substantial damage due to penetration of ions through the dielectric atop the semiconductor material. The second etching operation may take place in a reactor configured to produce an inductively coupled plasma. Both the first and second etching operations may themselves be multi-step, cyclic processes.

Integrated etch/clean for dielectric etch applications

An apparatus and method for manufacturing an interconnect structure to provide ohmic contact in a semiconductor device is provided. The method includes providing a semiconductor device, such as a transistor, comprising a substrate, a gate dielectric, a gate electrode, and source and drain regions in the substrate. An ultra-thin interfacial dielectric is deposited by chemical vapor deposition (CVD) over the source and drain regions, where the interfacial dielectric can have a thickness between about 3 &#x212b; and about 20 &#x212b;. The ultra-thin interfacial dielectric is configured to unpin the metal Fermi level from the source and drain regions. Other steps such as the deposition of a metal by CVD and the cleaning of the substrate surface can be performed in an integrated process tool without a vacuum break. The method further includes forming one or more vias through a pre-metal dielectric over the source and drain regions of the substrate.

CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications

A methods of forming a flash memory device are provided. The flash memory device comprises a silicon dioxide layer on a substrate and a silicon nitride layer that is formed on the silicon dioxide layer. The properties of the silicon nitride layer can be modified by any of: exposing the silicon nitride layer to ultraviolet radiation, exposing the silicon nitride layer to an electron beam, and by plasma treating the silicon nitride layer. A dielectric material is deposited on the silicon nitride layer and a conductive date is formed over the dielectric material. The flash memory device with modified silicon nitride layer provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device.

Method of forming flash memory with ultraviolet treatment

Growing community of inventors

Scotts Valley, CA, United States of America

Reza Arghavani