Texas Instruments Corporation

Sv Probe Pte. Ltd.

Reynaldo M Rincon

Richard W Arnold

Jerry J Broz

Lester L Wilson

Darvin R Edwards

James A Forster

Gregory Barton Hotchkiss

Michael F Chisholm

Son N Dang

Gerald Back

Cheryl Diane Hartfield

Lich Thanh Tran

Yee Hsun U

Scott W Mitchell

Gerard Laugier

Viswanathan Sundararaman

A method and apparatus for a flattened probe element wire is provided. A probe element wire includes a beam portion and a tip portion. At least a part of the tip portion is flattened. Flattened probe element wires may have greater z-direction height strength, thereby increasing maximum probe element wire z-direction vertical force. Flattened probe element wires may also have decreased variability in the flattened probe element wire tips. A probe card assembly may includes a substrate and a plurality of at least partially flattened probe element wires supported by the substrate. Such probe card assemblies may have an extended life and maintained within design parameters for a longer period of use.

Cantilever probe card

A probe card assemblage for simultaneously testing one or more integrated circuit chips including an interposer having on one surface a plurality of protruding contact elements for electrically contacting one or more chips of a wafer positioned atop a layer of compliant material, and arrayed in a pattern corresponding to a chip pads, a series of conductive vias through the electrically insulating interposer which connect the chip contact elements with an arrangement of leads terminating in a universal arrangement of connectors on the second surface, and a probe card with connectors mating to those on the interposer. The connectors on the interposer is secured are secured to those on the probe card, thereby providing a vertical probe assemblage which makes use of ultrasonic energy to minimize scrub or over travel. The universal probe card is specific to a tester configuration and common to a family of circuits to be tested.

Multiple-chip probe and universal tester contact assemblage

Apparatus and methods for testing conductive bumps or target test points on integrated circuits. A multiplicity of probes are extended through a support substrate. At least one of the multiplicity of probe locations include a second electrically isolated probe such that the test point is in contact with two probes. One of the two probes provides a voltage to the test point and the second probe sensing the voltage so as to provide a Kelvin connection.

Multiple contact vertical probe solution enabling Kelvin connection benefits for conductive bump probing

A probe card apparatus comprising a rigid substrate having thermal expansion characteristics near that of silicon, laminated with a flex film having laser patterned leads and contact pads, and contact elements comprising noble metals protruding from two major surfaces, the first mirroring the closely spaced chip pads, and the second aligned to the more generously spaced probe card pads, providing an accurate and reproducible, low cost, rapidly fabricated probe contact device, capable of contacting very high density bond pads in either area array or perimeter locations, of being electrically optimized, and readily maintained.

High density, area array probe card apparatus

An apparatus ( ) and method ( ) for predicting electrical property stability of a thin film or conductive substrate ( ) prior to multi-probe testing. The present invention utilizes a nanoindenter type device ( ) obtaining mechanical properties as a function of displacement depth and applied load into the bond pad surface to accurately predict electrical property stability of the entire substrate or sample under test. In addition, the present invention includes a nanoindenter type device ( ) including a second probe ( ) having the ability to measure localized electrical properties of the sample while obtaining the mechanical property measurements. This additional electrical measurement is correlated with the mechanical property measurements to accurately predict electrical property stability of the entire conductive substrate, preferably by predicting the presence of an unwanted material surface layer.

Combined electrical test and mechanical test system for thin film characterization

A high density probe card contact apparatus including a support block fitted into an opening in a probe card, and holding a plurality of fine tipped needles extending inward and below an opening in the center of the block. The needle tips are a noble metal integrally connected with a less costly conductive metal which forms the more widely spaced fingers of the needles, and which terminate in contacts to the probe card. Laser etching defines the fine needle pattern in a thin sheet of the two-metal composition which is secured to a polymeric film. The contact apparatus is assembled by positioning one or more sections of the polymer with needles on the support film.

High density probe card apparatus and method of manufacture

A probe card having reliable &ldquo;micro probe&rdquo; contacts which include a base and an angled probe tip fabricated as a single unit from a thin sheet of a conductive metal having high tensile and yield strength, and coated with a noble metal. The micro probes are secured into precisely dimensioned, and positioned locations on the card, and are electrically connected to traces on the card. Design of the micro probes includes not only the base and probe tip, but also locking features, a stand-off to prevent over compression, and a necked down stem feature for release from the support strap used in transporting and plating during the manufacturing processes.

Probe card with contact apparatus and method of manufacture

A conductive via pattern ( ) between the uppermost metal interconnect layer (M ) and next underlying metal interconnect layer (M ) in the bond pad areas strengthens the interlevel dielectric (ILD ) between metal layers (M and M ). The conductive via layer ( ) may, for example, comprise parallel rails ( ) or a grid of cross-hatch rails ( ). By spreading the stress concentration laterally, the conductive via layer ( ) inhibits micro-cracking from stress applied to the bond pad ( ).

Approach to structurally reinforcing the mechanical performance of silicon level interconnect layers

A method of fabricating a semiconductor device which includes providing a shaped bond pad, preferably rectangular or oval. A cavity followed by a hill are formed in the bond pad by performing a probe test at one end portion of the bond pad. Then a ball bond is formed on the bond pad remote and spaced from the cavity. The ball bond can extend onto the hill or be spaced from the hill. The bond pad preferably has a greater length than width and the cavity, hill and ball bond are disposed successively along the length of the bond pad. The length of the bond pad in the direction normal to the cavity, the hill and the ball bond is greater than the sum of the diameter of a probe tip with which a probe test will be made on the bond pad and the diameter of the ball bond.

Growing community of inventors

Richardson, TX, United States of America

Reynaldo M Rincon