International Business Machines Corporation

Globalfoundries Inc.

Freescale Semiconductor,inc.

Renee Tong Mo

Effendi Leobandung

Jeffrey W Sleight

Vijay Narayanan

Shreesh Narasimha

Sanghoon Lee

Anthony I Chou

Arvind Kumar

Michael Patrick Chudzik

Leland Chang

Isaac Lauer

Cheng-Wei Cheng

Takashi Ando

Judson Robert Holt

Amlan Majumdar

Martin Michael Frank

Wesley Charles Natzle

Brent A Wacaser

Yanning Sun

Christian Lavoie

Ravikumar Ramachandran

William K Henson

Mahadevaiyer Krishnan

John Rozen

Zhibin Ren

Jay William Strane

Randolph F Knarr

Michael Abramovich Gribelyuk

Oleg Gluschenkov

Dureseti Chidambarrao

Kern Rim

Richard Stephan Wise

Eduard Albert Cartier

John Albrecht Ott

Naim Moumen

Yaocheng Liu

Alexander Reznicek

Jeffrey P Gambino

Pouya Hashemi

Toshiharu Furukawa

Josephine B Chang

Kevin K Chan

Balasubramanian Pranatharthiharan

Keith Kwong Hon Wong

Cyril Cabral, Jr

Andres Bryant

Dominic Joseph Schepis

Pranita Kerber

Huiming Bu

Vamsi Krishna Paruchuri

Steven John Koester

Kathryn Turner Schonenberg

Sunfei Fang

Hongwen Yan

Ashima B Chakravarti

Edward P Maciejewski

Eric Peter Solecky

Xi Li

Oliver Desmond Patterson

Balasubramanian S Pranatharthi Haran

Atul Champaklal Ajmera

Horatio Seymour Wildman

Sadanand Vinayak Deshpande

Devendra K Sadana

Bruce Bennett Doris

Ghavam G Shahidi

Stephen W Bedell

Sivananda K Kanakasabapathy

Ying Di Zhang

Zhijiong Luo

James William Adkisson

Kirk David Peterson

Jeng-Bang Yau

Brian Joseph Greene

Sufi Zafar

Siddarth A Krishnan

Meikei Ieong

Richard Anthony Conti

Barry P Linder

Dae-Gyu Park

Henry K Utomo

Robert L Bruce

Huajie Chen

Alessandro Cesare Callegari

Werner A Rausch

Rishikesh Krishnan

Sebastian Ulrich Engelmann

Diane Catherine Boyd

Daniel J Jaeger

Todd Christopher Bailey

Ko-Tao Lee

Ying Li

Robert J Purtell

Troy Lawrence Graves-Abe

Ricardo Alves Donaton

Dan Mihai Mocuta

Michelle Leigh Steen

James Kenyon Schaeffer, Iii

Yue Ke

Kunal Mukherjee

A method for forming an overlap transistor includes forming a gate structure over a III-V material, wet cleaning the III-V material on side regions adjacent to the gate structure and plasma cleaning the III-V material on the side regions adjacent to the gate structure. The III-V material is plasma doped on the side regions adjacent to the gate structure to form plasma doped extension regions that partially extend below the gate structure.

III-V extension by high temperature plasma doping

A method of fabricating an n-type field effect transistor device (nFET) in a region of a wafer element is provided. The method includes forming a mandrel in the region and growing III-V semiconductor materials on the mandrel. The method also includes pulling the mandrel from a gate space in which a capped gate structure is formable and from source and drain (S/D) contact spaces and growing III-V semiconductor materials in the S/D contact spaces.

III-V CMOS co-integration

In one example, a method for fabricating a semiconductor device includes forming a mandrel comprising silicon. Sidewalls of the silicon are orientated normal to the &#x3c;111&#x3e; direction of the silicon. A nanowire is grown directly on at least one of the sidewalls of the silicon and is formed from a material selected from Groups III-V. Only one end of the nanowire directly contacts the silicon.

Growing Groups III-V lateral nanowire channels

Semiconductor devices and methods of forming the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region. The second semiconductor region is formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A semiconductor cap is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.

Distinct gate stacks for III-V-based CMOS circuits comprising a channel cap

A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

Semiconductor structure with integrated passive structures

Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A gate dielectric layer is formed over one or more of the first and second channel regions. A nitrogen-containing layer is formed on the gate dielectric layer. A gate is formed on the gate dielectric.

Patterned gate dielectrics for III-V-based CMOS circuits

Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A nitrogen-containing layer is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.

A method of forming a strained channel for a field effect transistor, including forming a sacrificial layer on a substrate, forming a channel layer on the sacrificial layer, forming a stressor layer on the channel layer, wherein the stressor layer applies a stress to the channel layer, forming at least one etching trench by removing at least a portion of the stressor layer, channel layer, and sacrificial layer, wherein the etching trench exposes at least a portion of a sidewall of the sacrificial layer, and separates the stressor layer, channel layer, and sacrificial layer into two or more stressor islands, channel blocks, and sacrificial slabs, and removing the sacrificial slabs to release the channel blocks from the substrate using a selective etch, wherein the channel blocks adhere to the substrate surface.

Fabrication of a strained region on a substrate

A semiconductor structure is provided that can be used for DNA sequencing detection. The semiconductor structure includes a doped epitaxial source semiconductor material structure located on a first portion of a semiconductor substrate and a doped epitaxial drain semiconductor material structure located on a second portion of the semiconductor substrate. A gate dielectric portion is located on a third portion of the semiconductor substrate and positioned between the doped epitaxial source semiconductor material structure and the doped epitaxial drain semiconductor material structure. A non-stick nucleotide, DNA and DNA polymerase material structure is located atop the doped epitaxial source semiconductor material structure and atop the doped epitaxial drain semiconductor material structure, wherein a cavity is present in the non-stick nucleotide, DNA and DNA polymerase material structure that exposes a topmost surface of the gate dielectric portion.

DNA sequencing detection field effect transistor

A method for use in forming a fin of a field-effect transistor includes: patterning a mandrel into a substrate at least by recessing portions of the substrate; forming dielectric material at least on the recessed portions of the substrate, wherein the dielectric material partially covers exterior sidewalls of the mandrel; forming a first buffer at least on a portion of the exterior sidewalls of the mandrel not covered by the dielectric material; forming a second buffer at least on exterior sidewalls of the first buffer; forming a semiconductor channel at least on the dielectric material, wherein at least the second buffer is between the channel and the mandrel; exposing interior sidewalls of at least the first buffer at least by removing the mandrel; and removing the first buffer and the second buffer without removing the channel.

Surface roughness of III-V fin formed on silicon sidewall by implementing sacrificial buffers

A method of forming high germanium content silicon germanium alloy fins with controlled insulator layer recessing is provided. A silicon germanium alloy (SiGe) layer having a first germanium content is provided on a surface of an insulator layer using a first condensation process. Following the formation of a hard mask layer portion on the SiGe layer, a second condensation process is performed to convert a portion of the SiGe layer into a SiGe fin of a second germanium content that is greater than the first germanium content and other portions of the SiGe layer into a shell oxide structure located on sidewalls of the SiGe fin. After forming a fin placeholder material, a portion of each shell oxide structure is removed, while maintaining a lower portion of each shell oxide structure at the footprint of the SiGe fin.

Method of forming high-germanium content silicon germanium alloy fins on insulator

Growing groups III-V lateral nanowire channels

Growing community of inventors

Briarcliff Manor, NY, United States of America

Renee Tong Mo