Infineon Technologies Ag

Reinhard Hess

Thorsten Meyer

Recai Sezi

Rainer Leuschner

Alexander Heinrich

Gerald Ofner

Gunther Mackh

Markus Menath

Katharina Umminger

Hannes Eder

Gabriel Maier

Franco Mariani

Gerhard Leschik

Andreas Bauer

A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements

A method includes providing a semiconductor wafer including multiple semiconductor chips, forming a first scribe line on a frontside of the semiconductor wafer, wherein the first scribe line has a first width and separates semiconductor chips of the semiconductor wafer, forming a second scribe line on the frontside of the semiconductor wafer, wherein the second scribe line has a second width and separates semiconductor chips of the semiconductor wafer, wherein the first scribe line and the second scribe line intersect in a crossing area which is greater than a product of the first width and the second width, and plasma etching the semiconductor wafer in the crossing area.

Semiconductor device and method for manufacturing a semiconductor device

A method of manufacturing a semiconductor package includes embedding a semiconductor chip in an encapsulant. First contact pads are formed on a first main face of the semiconductor package and second contact pads are formed on a second main face of the semiconductor package opposite the first main face. A diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d&#x2267;(8/25)x+142 &#x3bc;m, where x is a pitch of the second contact pads in micrometers.

Packaged semiconductor device with encapsulant embedding semiconductor chip that includes contact pads

A semiconductor package includes a semiconductor chip, an encapsulant embedding the semiconductor chip, first contact pads on a first main face of the semiconductor package and second contact pads on a second main face of the semiconductor package opposite to the first main face. The diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d&#x2267;(8/25)x+142 &#x3bc;m, wherein x is the pitch of the second contact pads in micrometers.

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Straubing, Germany

Reinhard Hess