Infineon Technologies Ag

Reimund Engl

Joachim Mahler

Michael Bauer

Heinrich Koerner

Werner Kanert

Michael Huettinger

Brigitte Ruehle

Jochen Dangelmaier

Francisco Javier Santos Rodriguez

Frank Hille

Andreas Walter

Antonio Vellei

Johann Gatterbauer

Rupert Fischer

Ralf Otremba

Recai Sezi

Anna Maltenberger

Henrik Ewe

Thomas Behrens

Bernd Rakow

Joerg Schumann

Thomas Weitz

Josef Hoeglauer

Klaus Schiess

Günter Schmid

Manfred Mengel

Rainald Sander

Hans-Joerg Timme

Dirk Meinhold

Marcus Halik

Hagen Klauk

Stefan Landau

Wae Chet Yong

Soon Lock Goh

Stanley Job Doraisamy

Norbert Urbansky

Alfred Vater

Robert Bergmann

Gerhard Deml

Norbert Mais

Boris Plikat

Alvin Wee Beng Tatt

Stephan Henneck

Wolfgang Kuebler

A method of forming an electrical contact is provided. The method may include depositing, by atomic layer deposition, a passivation layer over at least a region of a metal surface, wherein the passivation layer may include aluminum oxide, and electrically contacting the region of the metal surface with a metal contact structure, wherein the metal contact structure may include copper.

Chip package, method of forming a chip package and method of forming an electrical contact

A method of forming an electrical contact and a method of forming a chip package are provided. The methods may include arranging a metal contact structure including a non-noble metal and electrically contacting the chip, arranging a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

Method of forming an electrical contact and method of forming a chip package with a metal contact structure and protective layer

In various embodiments, methods for forming a chip package are provided. The chip package may include a chip comprising a chip metal surface, a metal contact structure electrically contacting the chip metal surface, a packaging material at least partially encapsulating the chip and the metal contact structure, and a chemical compound physically contacting the packaging material and at least one of the chip metal surface and the metal contact structure, wherein the chemical compound may be configured to improve an adhesion between the metal contact structure and the packaging material and/or between the chip metal surface and the packaging material, as compared with an adhesion in an arrangement without the chemical compound, wherein the chemical compound is essentially free from functional groups comprising sulfur, selenium or tellurium.

Method for forming a chip package with compounds to improve the durability and performance of metal contact structures in the chip package

In various embodiments, a chip package is provided. The chip package may include a chip comprising a chip metal surface, a metal contact structure electrically contacting the chip metal surface, a packaging material at least partially encapsulating the chip and the metal contact structure, and a chemical compound physically contacting the packaging material and at least one of the chip metal surface and the metal contact structure, wherein the chemical compound may be configured to improve an adhesion between the metal contact structure and the packaging material and/or between the chip metal surface and the packaging material, as compared with an adhesion in an arrangement without the chemical compound, wherein the chemical compound is essentially free from functional groups comprising sulfur, selenium or tellurium.

Chip package comprising a chemical compound and a method of forming a chip package comprising a chemical compound

In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

Chip package and method of forming a chip package with a metal contact structure and protective layer, and method of forming an electrical contact

In various embodiments, a chip package is provided. The chip package may include a chip including a chip metal surface, a metal contact structure electrically contacting the chip metal surface, and packaging material including a contact layer being in physical contact with the chip metal surface and/or with the metal contact structure; wherein at least in the contact layer of the packaging material, a summed concentration of chemically reactive sulfur, chemically reactive selenium and chemically reactive tellurium is less thanatomic parts per million.

Chip package and method of forming a chip package

A semiconductor device is disclosed. One embodiment includes a carrier, a semiconductor chip attached to the carrier, a first conducting line having a first thickness and being deposited over the semiconductor chip and the carrier and a second conducting line having a second thickness and being deposited over the semiconductor chip and the carrier. The first thickness is smaller than the second thickness.

Semiconductor device

In one embodiment, a method of forming a semiconductor device includes forming a metal line over a substrate and depositing an alloying material layer over a top surface of the metal line. The method further includes forming a protective layer by combining the alloying material layer with the metal line.

Protection layers for conductive pads and methods of formation thereof

A semiconductor device and method is disclosed. One embodiment provides a method comprising placing a first semiconductor chip on a carrier. After placing the first semiconductor chip on the carrier, an electrically insulating layer is deposited on the carrier. A second semiconductor chip is placed on the electrically insulating layer.

An integrated circuit device includes a semiconductor chip and a control chip at different supply potentials. A lead chip island includes an electrically conductive partial region and an insulation layer. The semiconductor chip is arranged on the electrically conductive partial region of the lead chip island and the control chip is cohesively fixed on the insulation layer.

Integrated circuit device and method for the production thereof

A semiconductor device includes a carrier, a semiconductor chip including an active area on a first face and a separate isolation layer applied to a second face, and an adhesion material coupling the isolation layer to the carrier with the second face facing the carrier.

Semiconductor device including isolation layer

A method for producing a power semiconductor module having surface mountable flat external contact areas is disclosed. At least one power semiconductor chip is fixed by its rear side on a drain external contact. An insulation layer covers the top side over the side edges of the semiconductor chip as far as the inner housing plane was a leaving free the source and gate contact areas on the top side of the semiconductor chip and also was partly leaving free the top sides of the corresponding external contacts.

Method for producing a power semiconductor module comprising surface-mountable flat external contacts

A semiconductor device is disclosed. One embodiment provides a device including a carrier, an electrically insulating layer applied onto the carrier, an adhesive layer applied to the electrically insulating layer. A first semiconductor chip applied to the adhesive layer.

Semiconductor device with a metallic carrier and two semiconductor chips applied to the carrier

A semiconductor module is disclosed. One embodiment provides a first semiconductor chip, a second semiconductor chip and a spacer. The first semiconductor chip has a depression at a first main surface. The spacer applied to the first main surface and at least partly fills the depression. The second semiconductor chip is applied to the spacer.

Semiconductor module

A semiconductor device includes a leadframe having a first face and an opposing second face, a portion of the first face defining a die pad, a diffusion barrier deposited on at least a portion of the die pad, and at least one chip coupled to the diffusion barrier.

Growing community of inventors

Wuppertal, Germany

Reimund Engl