Matsushita Electric Industrial Co., Ltd.

Reiko Hinogami

Hideo Nakagawa

Akio Misaka

Hisashi Watanabe

Eiji Tamaoka

Tadashi Tanimoto

Minoru Yamagiwa

Established is a mask pattern correcting technique for reducing the load to a mask CAD process and for ensuring the minimum dimension defined in an OPC process. A method comprises the steps of: measuring a line width of a mask pattern; extracting edges where the line width of the mask pattern is smaller than a predetermined dimension; generating a central geometrical object having a predetermined width relative to the center between the edges where the line width is smaller than the predetermined dimension; and replacing the portion of the mask pattern where the line width is smaller than the predetermined dimension with the central geometrical object. As a result, the mask pattern line width is changed into the predetermined with dimension of the central geometrical object. This reduces notably the number of geometrical object calculating steps that had been performed for each value of dimension on the basis of a correction table in the prior art, and thereby shortens the mask CAD processing time.

Mask pattern generating method and mask pattern generating apparatus

After depositing a metal film on an insulating film on a semiconductor substrate, a first interlayer insulating film is formed on the metal film. After forming first plug openings in the first interlayer insulating film by etching the first interlayer insulating film with a first mask pattern used as a mask, first connection plugs are formed by filling a first conducting film in the first plug openings. A second interlayer insulating film is formed on the first interlayer insulating film. After forming second plug openings respectively on the first connection plugs in the second interlayer insulating film by etching the second interlayer insulating film with a second mask pattern used as a mask, second connection plugs are formed by filling a second conducting film in the second plug openings. The metal film is etched by using at least the first connection plugs and the second connection plugs as a mask so as to form metal interconnects, and then, a third interlayer insulating film is formed on the metal interconnects so as to form an air gap between the metal interconnects.

Semiconductor device and method for fabricating the same

A photomask of this invention includes a main pattern part for forming a main pattern in a resist film and an alignment mark part for forming, in the resist film, an alignment accuracy determining mark not penetrating the resist film in section after development of the resist film.

Growing community of inventors

Kawabe-gun, Japan

Reiko Hinogami