Siemens Aktiengesellschaft

Infineon Technologies Ag

Intel Mobile Communications Gmbh

Intel Deutschland Gmbh

Qimonda Ag

Siemens Aktiengesell Schaft

Siemens Aktiengesellscaft

Osram Opto Semiconductor Gmbh Co. Ohg

Siemens Aktiengesesllschaft

Recai Sezi

Hellmut Ahne

Rainer Leuschner

Michael Sebald

Siegfried Birkle

Andreas Walter

Thorsten Meyer

Michael Keitmann

Klaus Lowack

Markus Brunnbauer

Anna Maltenberger

Eva Rissel

Eberhard Kuehn

Jens G Pohl

Klaus Pressel

Ralf Plieninger

Stephan Bradl

Horst Borndoerfer

Roland Gestigkeit

Juergen Beck

Horst Borndorfer

Gottfried Beer

Günter Schmid

Guenter Schmid

Gerald Ofner

Marcus Halik

Gerhard Maier

Reimund Engl

Hans-Dieter Feucht

Erwin Schmidt

Barbara Lehner

Reinhard Hess

Joerg Schumann

J&ouml;rg Haussmann

Andreas Weber

Kurt Geibel

Thomas Weitz

Kurt Hoffmann

Albert Hammerschmidt

Christine Dehm

Eberhard Kuhn

Ute Zschieschang

Tobias Noll

Ingo Gnüchtel

Horst Hartmann

G&uuml;nter Schmid

Wolfgang Radlik

Ann Dumoulin

Hans Jurgen Bestmann

Ewald G&uuml;nther

Joerg Haussmann

Eva-Maria Rissel

Stephan Brandl

Gunther Schmid

Hans-Juergen Bestmann

Hellmut Ahhe

Seigfried Birkle

Sueleyman Kocman

Robert Banfic

A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.

Workpiece with semiconductor chips, semiconductor device and method for producing a workpiece with semiconductor chips

A semiconductor device is disclosed. One embodiment includes a semiconductor substrate and at least two insulating elements located above the semiconductor substrate or above a mold compound embedding the semiconductor substrate. The at least two insulating elements have a first face facing the semiconductor substrate or the mold compound and a second face facing away from the semiconductor substrate or the mold compound. A conductive element for each of the at least two insulating elements extends from the first face of the insulating element to the second face of the insulating element.

Semiconductor device

A method of manufacturing a semiconductor package includes embedding a semiconductor chip in an encapsulant. First contact pads are formed on a first main face of the semiconductor package and second contact pads are formed on a second main face of the semiconductor package opposite the first main face. A diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d&#x2267;(8/25)x+142 &#x3bc;m, where x is a pitch of the second contact pads in micrometers.

Packaged semiconductor device with encapsulant embedding semiconductor chip that includes contact pads

Structure for electrostatic discharge in embedded wafer level packages

A polymer layer is generated on a wafer. The wafer is then separated into semiconductor chips. At least two semiconductor chips are placed on a carrier with the polymer layer facing the carrier. The at least two semiconductor chips are covered with an encapsulating material to form an encapsulant. The carrier is removed from the encapsulant, and the encapsulant and the polymer layer are thinned.

Semiconductor package and multichip arrangement having a polymer layer and an encapsulant

A semiconductor package includes a semiconductor chip, an encapsulant embedding the semiconductor chip, first contact pads on a first main face of the semiconductor package and second contact pads on a second main face of the semiconductor package opposite to the first main face. The diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d&#x2267;(8/25)x+142 &#x3bc;m, wherein x is the pitch of the second contact pads in micrometers.

Stacked semiconductor chips are disclosed. One embodiment provides a method including a first substrate having a first surface and an opposing second surface. The first substrate includes an array of first connection elements on the first surface of the first substrate. A second substrate has a first surface and an opposing second surface. The second substrate includes an array of second connection elements on the first surface of the second substrate. The first connection elements is attached to the second connection elements; and is thinning at least one of the first substrate and the second substrate after the attachment of the first connection elements to the second connection elements.

Stacked semiconductor chips

A semiconductor device including a chip including an integrated circuit, a conductive layer, a copolymer layer and metal elements. The conductive layer is disposed over the chip and electrically coupled to the integrated circuit. The copolymer is disposed on the conductive layer. The metal elements are electrically coupled to the conductive layer via through-connects in the copolymer layer.

Semiconductor device including a copolymer layer

A memory arrangement includes: a first line for applying a reference voltage, a second line for applying an operating voltage, and a plurality of resistive memory elements, each element includes a resistive memory cell and a MOS memory cell selection transistor. A NOR memory arrangement is configured with each memory element including the resistive memory cell and selection transistor connected in series with the transistor connected to the first line, and the memory cell connected to the second line. A NAND memory arrangement is configured with a series of resistive memory elements forming a chain with each memory element including the resistive memory cell and selection transistor connected in parallel. The chain is connected to the first line disposed on a side of the memory cells facing the selection transistors and the second line disposed on a side of the memory cells which is remote from the selection transistors.

NOR and NAND memory arrangement of resistive memory elements

A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also includes an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. In the molding compound a contact via is arranged.

Workpiece with semiconductor chips and molding, semiconductor device and method for producing a workpiece with semiconductors chips

The invention relates to a process for the metallization of an insulator and/or a dielectric, wherein the insulator is firstly activated, it is subsequently coated with another insulator and the latter is patterned, then the first is seeded and lastly metallized.

Method for the metalization of an insulator and/or a dielectric

The present invention relates to a process for producing a porous layer adhering to a substrate, which comprises the steps:

Method for producing a porous coating

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Roettenbach, Germany

Recai Sezi