International Business Machines Corporation

Other

Raymond R Horton

Michael J Palmer

Ismail C Noyan

Alphonso Philip Lanzetta

John Ulrich Knickerbocker

Edmund Juris Sprogis

Cornelia K Tsang

Chandrasekhar Narayan

Paul Stephen Andry

Leena Paivikki Buchwalter

Mark F Bregman

Ho-Ming Tong

Bernardo Hernandez

Bing Dang

Jon Alfred Casey

Steven Lorenz Wright

Mark B Ritter

Pedro A Chalco

Frederick G Weindelmayer

Sampath Purushothaman

Robert K Montoye

Lawrence Shungwei Mok

George Frederick Walker

David Lee Rath

Thomas Mario Cipolla

Bruce Kenneth Furman

Brian Richard Sundlof

Sherif Ahmed Goma

Kurt R Grebe

Harry R Bickford

Linda C Matthew

Joseph Maryan Milewski

William D Brewer

Bernie Hernandez

Joana Maria

Hussain Shaukatulla

John C Zyzo

Daniel C Edelstein

Peter Alfred Gruber

Kevin Shawn Petrarca

Gareth Geoffrey Hougham

Richard Paul Volant

Xiao Hu Liu

Donald Francis Canaperi

Eric D Perfecto

Michael Wayne Lane

Chirag Suryakant Patel

Tien-Jen Cheng

Michelle Leigh Steen

Kevin Wilson Warren

Matthew J Farinelli

Ronald Dean Goldblatt

Robert J Polastre

Michael Berger

James Anthony Tornello

Philip Murphy

William Edward Pence, Iv

Anurag Jain

Paul M Alt

William E Pence, Iv

Benal Lee Owens, Jr

Chiraq S Patel

Ismail C Novan

Ismail Gevdet Noyan

Die stacks and methods of making die stacks with very thin dies are disclosed. The die surfaces remain flat within a 5 micron tolerance despite the thinness of the die and the process steps of making the die stack. A residual flux height is kept below 50% of the spacing distance between adjacent surfaces or structures, e.g. in the inter-die spacing.

Method of forming thin die stack assemblies

Thinned die stack

A transfer process for bonding a solderable device to a solderable firsl substrate having a first oxidized surface comprises placing the solderable device proximate to the first substrate in a reducing chamber, where the first surface cannot be visually observed. We place a second substrate having a second oxidized surface in the chamber in a way to visually observe the second surface. Selecting the first substrate and the second substrate so that the reduction of the second surface correlates with the reduction of the first surface provides an indication of the degree of reduction of the first surface. Introducing a reducing agent into the chamber under reducing conditions reduces the surfaces which we track by irradiating and observing the second surface; evaluate any change in the second surface during irradiation and correlate the change with first surface reduction. When sufficiently reduced, we solder the first substrate to the device.

Process for mapping formic acid distribution

A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided.

Laser release process for very thin Si-carrier build

Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device includes at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device including at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein includes the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

Techniques for providing decoupling capacitance

Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or mole vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; aligning the placement guide to an integrated circuit chip position on the module substrate; fixing the placement guide to the module substrate; placing an integrated circuit chip in the guide opening, sidewalls of the placement guide opening constraining electrically conductive bonding structures on bottom surface of the integrated circuit chip to self-align to an electrically conductive module substrate contact pad on the top surface of the module substrate in the integrated circuit chip position; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.

Method for precision assembly of integrated circuit chip packages

A method for filling vias, and in particular initially blind vias, in a wafer, and various apparatus for performing the method, comprising evacuating air from the vias; trapping at least a portion of the wafer and a paste for filling the vias between two surfaces; and pressurizing the paste to fill the vias.

Method and apparatus for filling vias

A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

Silicon chip carrier with conductive through-vias and method for fabricating same

Sealing a via using a soventless, low viscosity, high temperature stable polymer or a high solids content polymer solution of low viscosity, where the polymeric material is impregnated within the via at an elevated temperature. A supply chamber is introduced to administer the polymeric material at an elevated temperature, typically at a temperature high enough to liquefy the polymeric material. The polymeric material is introduced through heated supply lines under force from a pump, piston, or a vacuum held within said supply chamber.

Materials and method to seal vias in silicon substrates

The invention provides a wiring conductor for densely packed electronic apparatus, on which there is a supporting body of a material with randomly intertwined and fused filaments with spacing for being permeated by a coolant. The filamentary body material in addition may have imparted thereto the physical properties of interdependent density and permeability, noncorrosiveness and electrical conductivity.

Lightweight electronic equipment conductor with coolant permeable support

Growing community of inventors

Dover Plains, NY, United States of America

Raymond R Horton