Intel Corporation

Ravindranath Vithal Mahajan

Debendra Mallik

Robert L Sankman

Nitin A Deshpande

Digvijay Ashokkumar Raorane

Omkar G Karhade

Sujit Sharan

John Stephen Guzek

Aleksandar Aleksov

Shawna M Liff

Srinivas V Pietambaram

Dheeraj R Subbareddy

Md Altaf Hossain

Ankireddy Nalamalpu

Je-Young Chang

Rajasekaran Swaminathan

Mitul Bharat Modi

Bharat P Penmecha

Brian S Doyle

Adel A Elsherbini

Gregg William Baeckler

Sanka Ganesan

Wilfred Gomes

Ram S Viswanath

Paul R Start

Feras Eid

Mark T Bohr

Chia-Pin Chiu

Rajat Agarwal

Ravi Prakash Gutala

Scott J Weber

Rajesh Kumar

Aravind Raghavendra Dasu

Robert Starkston

Sandeep B Sane

Sriram Srinivasan

Ling Liao

Xiaoqian Li

Andrew Alduino

Christopher J Nelson

Stefan Rusu

Donald S Gardner

Eric Jin Li

Brandon C Marin

Sairam Agraharam

James Chris Matayabas, Jr

Amruthavalli Pallavi Alur

Jeremy D Ecton

Yikang Deng

Chandra Mohan Jha

Donald Tiendung Tran

Edvin Cetegen

Suddhasattwa Nad

Vladimir K Tamarkin

Srikant Nekkanty

Sergio Antonio Chan Arguedas

Deepak Kulkarni

Nicholas Neal

Kyle Jordan Arrington

Kelly P Lofgreen

Aastha Uppal

Ken P Hackenberg

David Hui

Ian A Young

Henning Braunisch

Kemal Aygun

Kristof Darmawikarta

Rahul N Manepalli

James E Jaussi

Zhiguo Qian

Michael T Crocker

Alan M Myers

Nachiket R Raravikar

Sarah E Kim

R Scott List

James G Maveety

James D Williams

Ravi S Prasher

John C Johnson

Tarek A Ibrahim

Andrew Paul Collins

Quat T Vu

Dingying David Xu

Nicholas S Haehn

Dae-Woo Kim

Phil Geng

Yidnekachew S Mekonnen

Manish Dubey

Yiqun Bai

Kuang C Liu

Kevin J Haley

Devdatta P Kulkarni

Charles A Gealer

Weihua Tang

Christopher M Pelto

Matthew L Tingey

Tolga Acikalin

Arnab Sarkar

Mohammad Enamul Kabir

Raanan Sover

Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate, and a die coupled to the package substrate. In an embodiment, the electronic package further comprises a stiffener on the package substrate surrounding the die. In an embodiment, the stiffener is a ring with one or more corner regions and one or more beams. In an embodiment, each beam is between a pair of corner regions, and the one or more corner regions have a first thickness and the one or more beams have a second thickness that is greater than the first thickness.

BGA stiffener attachment with low Eolife adhesive strength at high solder joint stress area generated from enabling load

Stacked die assemblies having a moisture sealant layer according to embodiments are described herein. A microelectronic package structure having a first die with a second and an adjacent third die on the first die. Each of the second and third die comprise hybrid bonding interfaces with the first die. A first layer is on a region of the first die adjacent sidewalls of the second and the third dies, and adjacent an edge portion of the first die. The first layer comprises a diffusion barrier material A second layer is over the first layer, the second layer, wherein a top surface of the second layer is substantially coplanar with the top surfaces of the second and third dies. The first layer provides a hermetic moisture sealant layer for stacked die package structures.

Moisture seal coating of hybrid bonded stacked die package assembly

Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer including an insulating material, wherein the PIC is embedded in the insulating material with an active surface facing up; a conductive pillar in the first layer; an integrated circuit (IC) in a second layer on the first layer, wherein the second layer includes the insulating material and the IC is embedded in the insulating material, and wherein the IC is electrically coupled to the active surface of the PIC and the conductive pillar; an optical component optically coupled to the active surface of the PIC; and a hollow channel surrounding the optical component, the hollow channel extending from the active surface of the PIC through the insulating material in the second layer.

Photonic integrated circuit packaging architectures

An electronic assembly, such as an integrated circuit package, may be formed comprising a package substrate and a photonic integrated circuit device attached thereto, wherein the package substrate includes a heat dissipation structure disposed therein. A back surface of the photonic integrated circuit device may thermally coupled to the heat dissipation structure within the package substrate for the removal of heat from the photonic integrated circuit device, which allows for access to an active surface of the photonic integrated circuit device for the attachment of fiber optic cables and eliminates the need for a heat dissipation device to be thermally attached to the active surface of the photonic integrated circuit device.

Heat dissipation structures for optical communication devices

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

Interconnect architecture with silicon interposer and EMIB

Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

Heterogeneous nested interposer package for IC chips

Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.

Nested architectures for enhanced heterogeneous integration

A two-phase immersion cooling system for an integrated circuit assembly may be formed utilizing boiling enhancement structures formed on or directly attached to heat dissipation devices within the integrated circuit assembly, formed on or directly attached to integrated circuit devices within the integrated circuit assembly, and/or conformally formed over support devices and at least a portion of an electronic board within the integrated circuit assembly. In still a further embodiment, the two-phase immersion cooling system may include a low boiling point liquid including at least two liquids that are substantially immiscible with one another.

Immersion cooling for integrated circuit devices

An electronic substrate may be fabricated having a dielectric material, metal pads embedded in the dielectric material with co-planar surfaces spaced less than one tenth millimeter from each other, and a metal trace embedded in the dielectric material and attached between the metal pads, wherein a surface of the metal trace is non-co-planar with the co-planar surfaces of the metal pads at a height of less than one millimeter, and wherein sides of the metal trace are angled relative to the co-planar surfaces of the metal pads. In an embodiment of the present description, an embedded angled inductor may be formed that includes the metal trace. In an embodiment, an integrated circuit package may be formed with the electronic substrate, wherein at least one integrated circuit devices may be attached to the electronic substrate. Other embodiments are disclosed and claimed.

Angled inductor with small form factor

An electronic package includes an interposer having an interposer substrate, a cavity that passes into but not through the interposer substrate, a through interposer via (TIV) within the interposer substrate, and an interposer pad electrically coupled to the TIV. The electronic package includes a nested component in the cavity, wherein the nested component includes a component pad coupled to a through-component via. A core via is beneath the nested component, the core via extending from the nested component through the interposer substrate. A die is coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect.

Nested interposer with through-silicon via bridge die

A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.

Programmable logic device with fine-grained disaggregation

A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

IC package including multi-chip unit with bonded integrated heat spreader

Photonic packages and device assemblies that include photonic integrated circuits (PICs) coupled to optical lenses on lateral sides of the PICs. An example photonic package comprises a package support, an integrated circuit (IC), an insulating material, a PIC having an active side and a lateral side substantially perpendicular to the active side. At least one optical structure is on the active side. A substantial portion of the active side is in contact with the insulating material, and the PIC is electrically coupled to the package support and to the IC. The photonic package further includes an optical lens coupled to the PIC on the lateral side. In some embodiments, the photonic package further includes an interposer between the PIC or the IC and the package support.

Photonic integrated circuit packaging architecture

An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the bridge die. The bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

Embedded bridge die with through-silicon vias

Growing community of inventors

Chandler, AZ, United States of America

Ravindranath Vithal Mahajan