Motorola Corporation

Freescale Semiconductor,inc.

Ravindranath Droopad

Zhiyi Jimmy Yu

Jamal Ramdani

Kurt W Eisenbeiser

Matthias Passlack

Jun J Wang

Yong Liang

William J Ooms

Jonathan K Abrokwah

Jerald A Hallmark

Yi Wei

Corey D Overgaard

Jeffrey M Finder

Lyndee L Hilt

Yu Wang

Xiaoming Hu

Daniel S Marshall

Hao Li

Alexander A Demkov

Jay A Curless

Nada El-Zein

Karthik Rajagopalan

John L Edwards, Jr

Ramoothy Ramesh

James Bradley Craigo

Ramamoorthy Ramesh

Brian Bowers

Dirk C Jordan

Zhiyi Yi

Zhiyi (Jimmy) Yu

Xiao M Hu

An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.

Insulated gate field effect transistors

An improved insulated gate field effect device () is obtained by providing a substrate () desirably comprising a III-V semiconductor, having a further semiconductor layer () on the substrate () adapted to contain the channel () of the device () between spaced apart source-drain electrodes () formed on the semiconductor layer (). A dielectric layer () is formed on the semiconductor layer (). A sealing layer () is formed on the dielectric layer () and exposed to an oxygen plasma (). A gate electrode () is formed on the dielectric layer () between the source-drain electrodes (). The dielectric layer () preferably comprises gallium-oxide () and/or gadolinium-gallium oxide (), and the oxygen plasma () is preferably an inductively coupled plasma. A further sealing layer () of, for example, silicon nitride is desirably provided above the sealing layer (). Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.

Method for forming an insulated gate field effect device

A method of forming a semiconductor structure includes forming a channel layer; forming a superlattice barrier layer overlying the channel layer, and forming a gate dielectric overlying the superlattice barrier layer. The superlattice barrier layer includes alternating first and second layers of barrier material. In addition, the superlattice barrier layer is configured for increasing a transconductance of the semiconductor device by at least a factor of three over a semiconductor device absent such superlattice barrier layer.

MOSFET device featuring a superlattice barrier layer and method

A method of forming a portion () of a compound semiconductor MOSFET structure comprises forming a compound semiconductor layer structure () and an oxide layer () overlying the same. Forming the compound semiconductor structure () includes forming at least one channel material () and a group-III rich surface termination layer () overlying the at least one channel material. Forming the oxide layer () includes forming the oxide layer to overlie the group-III rich surface termination layer and comprises one of (a) depositing essentially congruently evaporating oxide of at least one of (a(i)) a ternary oxide and (a(ii)) an oxide more complex than a ternary oxide and (b) depositing oxide molecules, with use of at least one of (b(i)) a ternary oxide and (b(ii)) an oxide more complex than a ternary oxide.

MOSFET structure and method of manufacture

A method of forming a III-V compound semiconductor structure () comprises providing a III-V compound semiconductor substrate including a semi-insulating substrate () having at least one epitaxial layer formed thereon and further having a gate insulator () overlying the at least one epitaxial layer. The at least one epitaxial layer formed on the semi-insulating substrate comprises an epi-structure suitable for use in the formation of a channel of a III-V compound semiconductor MOSFET device, wherein the channel () having a first polarity. The method further comprises forming a charge layer () at a surface of the gate insulator, the charge layer having a second polarity, wherein the second polarity is opposite to the first polarity.

III-V compound semiconductor device with a surface layer in access regions having charge of polarity opposite to channel charge and method of making the same

A method of forming a dielectric layer structure on a supporting semiconductor structure having a first surface comprises providing a first beam of oxide; depositing a first layer of oxide on the first surface of the supporting semiconductor structure using the first beam of oxide, wherein the first layer of oxide has a second surface; terminating the first beam of oxide, and concurrently providing a second beam of oxide, a beam of metal and a beam of oxygen, wherein the first and second beams of oxide are separate and distinct beams of oxide; and depositing a second layer of oxide on the second surface simultaneously using the second beam of oxide, the beam of metal, and the beam of oxygen.

Method of forming an oxide layer on a compound semiconductor structure

High quality epitaxial layers of monocrystalline oxide materials () can be grown overlying monocrystalline substrates () such as large silicon wafers. The monocrystalline oxide layer () comprises a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer () of silicon oxide. The amorphous interface layer serves as a decoupling layer between the substrate and the buffer layer so that the substrate and the buffer is crystal-graphically, chemically, and dielectrically decoupled. In addition, high quality epitaxial accommodating buffer layers may be formed overlying vicinal substrates using a low pressure, low temperature, alkaline-earth metal-rich process.

Method for fabricating semiconductor structures on vicinal substrates using a low temperature, low pressure, alkaline earth metal-rich process

High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Heterojunction tunneling diodes and process for fabricating same

A dielectric layer comprised of lanthanum, lutetium, and oxygen that is formed between two conductors or a conductor and a substrate. In one embodiment, the dielectric layer is formed over the substrate without the need for an additional interfacial layer. In another embodiment, the dielectric layer is graded with respect to the lanthanum or lutetium content or in the alternative, may include aluminum. In yet another embodiment, an insulating layer is formed between the conductor or substrate and the dielectric layer or between both the conductor and substrate and the dielectric layer. The dielectric layer is preferably formed by molecular beam epitaxy, but can also be formed by atomic layer chemical vapor deposition, physical vapor deposition, organometallic chemical vapor deposition or pulsed laser deposition.

High K dielectric film

High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same

A semiconductor structure exhibiting reduced leakage current is formed of a monocrystalline substrate () and a strained-layer heterostructure (). The strained-layer heterostructure has a first layer () formed of a first monocrystalline oxide material having a first lattice constant and a second layer () formed of a second monocrystalline oxide material overlying the first layer and having a second lattice constant. The second lattice constant is different from the first lattice constant. The second layer creates strain within the oxide material layers, at the interface between the first and second oxide material layers of the heterostructure, and at the interface of the substrate and the first layer, which changes the energy band offset at the interface of the substrate and the first layer.

Semiconductor structure exhibiting reduced leakage current and method of fabricating same

Circuit () has a dual layer gate dielectric () formed over a semiconductor substrate (). The gate dielectric includes an amorphous layer () and a monocrystalline layer (). The monocrystalline layer typically has a higher dielectric constant than the amorphous layer.

Semiconductor device and method

High quality monocrystalline metal oxide layers are grown on a monocrystalline substrate such as a silicon wafer. The monocrystalline metal oxide is grown on the silicon substrate at a temperature low enough to prevent deleterious and simultaneous oxidation of the silicon substrate. After a layer of 1-3 monolayers of the monocrystalline oxide is grown, the growth is stopped and the crystal quality of that layer is improved by a higher temperature anneal. Following the anneal, the thickness of the layer can be increased by restarting the low temperature growth. An amorphous silicon oxide layer can be grown at the interface between the monocrystalline metal oxide layer and the silicon substrate after the thickness of the monocrystalline oxide reaches a few monolayers.

Method for growing a monocrystalline oxide layer and for fabricating a semiconductor device on a monocrystalline substrate

High quality epitaxial layers of monocrystalline perovskite materials () can be grown overlying monocrystalline substrates () such as gallium arsenide wafers by forming a metal template layer () on the monocrystalline substrate. The structure includes a metal-containing layer () to mitigate unwanted oxidation of underlying layers and a low-temperature seed layer () that prevents degradation of an epitaxial layer () during growth of the perovskite layer ().

Compound semiconductor structure including an epitaxial perovskite layer and method for fabricating semiconductor structures and devices

A ferromagnetic semiconductor structure is provided. The structure includes a monocrystalline semiconductor substrate and a doped titanium oxide anatase layer overlying the semiconductor substrate.

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Chandler, AZ, United States of America

Ravindranath Droopad