Qualcomm Incorporated

Ravindranath Doddi

Santhosh Reddy Akavaram

Prakhar Srivastava

Umamaheshwaran V

Lekhya Pavani Godavarthi

Harinatha Reddy Ramireddy

Afreen Haider

Ravi Kumar Sepuri

Madhu Yashwanth Boenapalli

Surendra Paravada

Sai Praneeth Sreeram

Yogananda Rao Chillariga

Rajendra Varma Pusapati

Vinod Kumar Kuruma

James Lionel Panian

Ramacharan Sundararaman

Sonali Jabreva

Sai Sreeja Mukka

Aspects relate to variable link width in two directions for a main band chip module connection. In one aspect, a different set of data lines is active for transmit and receive data lines. In one example a method includes sending an enable request from a module of a first die to a module partner of a second die through a sideband to operate a main band of a die-to-die connection that connects the first die module to the second die module partner at a specified link width, the specified link width having a specified set of data lines of the main band. An enable response is received from the module partner through the sideband to operate the main band at the specified link width and data is communicated with the module partner through the main band using the specified link width in response to receiving the enable response.

Variable link width in two directions for main band chip module connection

Aspects of the disclosure provide techniques for retransmitting transaction layer packets (TLPs) for which a negative acknowledgment (NACK) is received without retransmitting previously transmitted TLPs that are correctly received, yet out-of-sequence, by a receiver. A receiver (e.g., a receiving link partner) can provide a transmitter (e.g., a transmitting link partner) with a NACK that includes a starting sequence number (SSN) and an ending sequence number (ESN), which can notify the transmitter about the packets for retransmission and/or packets that can be purged from a transmit buffer of the transmitter.

Flow control between peripheral component interconnect express devices

Various embodiments include methods and devices for implementing Universal Chiplet Interconnect Express (UCIe) link configuration for multi-module chiplets of a computing device. Embodiments may include transitioning a UCIe link in an active state having a first sideband that is active to the UCIe link in a reset state, and initializing at least one sideband for the UCIe link that is a different functional sideband of a multi-module chiplet than the first sideband following the reset state of the UCIe link. Embodiments may include reading sideband data configured to represent a functional sideband of the multi-module chiplet, and initializing the functional sideband as the at least one sideband. Embodiments may include reading sideband data configured to represent at least two functional sidebands of the multi-module chiplet, and initializing at least one functional sideband of the at least two functional sidebands as the at least one sideband.

Mechanism to improve the reliability of sideband in chiplets

A Peripheral Component Interconnect Express (PCIe) system and method achieve reduced latency and improved performance by reconfiguring the PCIe link to use an increased number of lanes for retransmitting data packets held in a replay buffer if one or more data packets transmitted by the TX device are flagged as not acknowledged (NACK) by the RX device. Before retransmitting the NACK-flagged packet(s), the link is reconfigured to use a greater number of lanes, preferably the maximum number of lanes that are available for use, and then the NACK-flagged packet(s) is retransmitted using the greater number of lanes until successful receipt of the NACK-flagged packets has been acknowledged by the RX device. Once the NACK-flagged packet(s) is successfully received by the RX device, the link is reconfigured to use the previous number of lanes and operations of the link resume using the previous number of lanes.

Systems and methods for reducing latency and improving performance in a peripheral component interconnect express (PCIe) system

A Peripheral Component Interconnect Express (PCIe) system and method achieve reduced power consumption and latency. When the link transitions from an active functional state in which the link has a first configuration of N active lanes to a power-saving state, the number of active lanes is collapsed such that M of the N lanes are maintained in an active power-saving state and P of the N lanes are maintained in an electrically idle state, where M, N and P are positive integers and N>P>M. The reduction in lane width reduces power consumption. Bit values specifying the current link configuration can be saved in a control register and read and compared to bit values contained in a link control register before transitioning back to the active functional state. If the bit values match, the active functional state is resumed directly from the recovery state, thereby reducing latency.

Systems and methods for reducing latency and power consumption in a peripheral component interconnect express (PCIe) system

A method for managing an interconnection between chiplets includes initiating sideband link training that includes transmitting a training pattern over each of a plurality of link configurations, where each link configuration includes a sideband data line and a sideband clock line. The method further includes suspending the sideband link training before completion of the sideband link training when the training pattern is transmitted over a first sideband link configuration without error, designating a sideband data line and a sideband clock line in the first sideband link configuration as a functional pair, and initiating mainband link training using the functional pair to communicate link state and status information.

Mechanism to improve link initialization time

Aspects relate to reduced training for main band chip module interconnection clock lines. In one example a method includes sending iterations of a first training pattern from a module of a first die to a module partner of a second die on a first main band clock line of a die-to-die connection, the die-to-die connection including a sideband, a main band comprising the first main band clock line, and at least one data line supported by at least the first main band clock line. An automatic result is received from the module partner through the sideband prior to completion of the iterations of the first training pattern, the automatic result indicating successfully receiving the training pattern. Data is communicated with the module partner through the main band using at least the first main band clock line in response to receiving the automatic result.

Reduced training for main band chip module interconnection clock lines

Aspects relate to an expanded data link width for a chip connection. In one example a sideband transmitter of a module of a first die is configured to send an expanded data link width enable request to a module partner through a sideband of a die-to-die connection to set an expanded data link width of a main band of the die-to-die connection. The expanded data link width includes data lines of the main band and redundant data lines of the main band reconfigured as data lines. A sideband receiver of the module is configured to receive an expanded data link width enable response from the module partner through the sideband to set the expanded data link width of the main band. A main band transmitter is configured to communicate data with the module partner through the main band using the expanded data link width.

Expanded data link width for main band chip module connection in alternate modes

Various embodiments include methods and devices for implementing a Peripheral Component Interconnect Express (PCIe) link configuration by a computing device. Embodiments may include selecting, by a PCIe device, a predetermined PCIe link speed based on a PCIe link configuration mode of a PCIe system of a plurality of PCIe link configuration modes of the PCIe system, and selecting, by the PCIe device, a PCIe link width of one lane for configuring the PCIe link. Embodiments may include selecting a PCIe link speed level lower than a current PCIe link speed in response to a reliability indicator exceeding a reliability threshold for a first PCIe link configuration mode. Embodiments may include selecting a maximum PCIe link speed for the PCIe link for a second PCIe link configuration mode. Embodiments may include increasing the PCIe link width in response to a requested bandwidth exceeding a configuration bandwidth of the PCIe link.

Mechanism to enhance PCIe generation switching

Aspects relate to single clock lane operation for a main band of a die-to-die connection. In one aspect, a single clock mode is enabled. A method includes sending a switch to single clock mode request from a module of a first die to a module partner of a second die through a sideband to request to enable a single clock mode of a main band of a die-to-die connection that connects the first die module to the second die module partner. A switch to single clock mode response is received from the module partner through the sideband to enable the single clock mode and data is communicated with the module partner through the main band in the single clock mode using a functional clock.

Single clock lane operation for a main band of a die-to-die connection

Various embodiments include methods and devices for implementing a Peripheral Component Interconnect Express (PCIe) link state transition by a computing device. Embodiments may include comprising retrieving, by a PCIe controller, PCIe link configuration data from a memory for a PCIe link in a fast recovery low power state of a link training status and state machine (LTSSM), and re-initializing, by the PCIe controller, the PCIe link using the PCIe link configuration data retrieved from the memory. Embodiments may further include maintaining the PCIe link configuration data in the memory for the PCIe link in the fast recovery low power state of the LTSSM by providing auxiliary power to PCIe configuration registers for the PCIe controller.

Mechanism to reduce exit latency for deeper power saving modes L2 in PCIe

Aspects relate to lane failure recovery for a data link having multiple lanes labeled in a contiguous sequence. In one aspect, a failure of a failed lane of the data link is detected. Working lanes of the data link are then detected. A set of contiguous working lanes of the data link are selected, and an operational link as including the selected set of contiguous working lanes is defined. A start address of the operational link is identified and stored in a configuration register. Data traffic is transmitted on the operational link.

Data rate increase for faulty lane recovery in multiple lane data links

A new peripheral component interconnect express (PCIe) link state can enhance power saving capabilities of a PCIe link operating in a flow control unit (FLIT) mode. A device can operate a data link with a host in a FLIT mode using fixed-sized packets, the data link being in a partial width link state (PLS) in which a first set of lanes of the data link are in an electrical idle state and a second set of lanes of the data link are in an active state available for data traffic with the host. The device can transition one or more lines of the second set of lanes from the PLS to a partial width standby link state (PSLS) in which the one or more lines of the second set of lanes are in a standby state that has lower power consumption than the active state.

Power management for peripheral component interconnect

Aspects relate to link speed for a peripheral component interconnect. In one aspect, an apparatus includes an interface circuit configured to provide an interface with a multiple lane data link, the data link having a first set of lanes in an active state and a second set of lanes in an idle state and a controller. The controller is configured to receive a request at the controller to change a data rate of the data link to a requested data rate, change the second set of lanes from an idle state to an active state, train the second set of lanes to the requested data rate, transfer data traffic from the first set of lanes to the second set of lanes after the training, and transmit the data traffic on the second set of lanes.

Latency reduction for link speed switching in multiple lane data links

Aspects relate to power management for a peripheral component interconnect. Transmit traffic activity may be monitored for a peripheral component interconnect express (PCIe) link. Receive traffic activity may also be monitored for the link A first power of transmit lines of the link is managed as a transmit group in accordance with the transmit traffic activity. A second power of the receive lines of the link are managed as a receive group in accordance with the receive traffic activity. The first power of the transmit lines is managed independently of the second power of the receive lines.

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Hyderabad Telangana, India

Ravindranath Doddi