Globalfoundries Inc.

Globalfoundries U.S. Inc.

International Business Machines Corporation

Advanced Micro Devices Corporation

Globalfoundries Singapore Pte. Ltd.

Samsung Electronics Co., Ltd.

Infineon Technologies Ag

Chartered Semiconductor Manufacturing Ltd (corporation)

Infineon Technologies North America Corp.

Toshiba America Electronic Components, Inc.

Globalfoundries Singapore Pte, Lte.

Ravi Prakash Srivastava

Sunil Kumar Singh

Akshey Sehgal

Hsueh-Chung Chen

Terry Allen Spooner

Sipeng Gu

Mark Alexander Zaleski

Sohan Singh Mehta

Brendan O'Brien

Sean Reidy

Yusheng Bian

Jiehui Shu

Shesh Mani Pandey

Nicholas V Licausi

Cung D Tran

Somnath Ghosh

Rui Chen

Zhiguo Sun

Xintuo Dai

Craig Child

Xinyuan Dou

Sanggil Bae

Teck Jung Tang

Dongyue Yang

Minghao Tang

Martin O'Toole

Md Motasim Bellah

Pavan Kumar Chinthamanipeta Sripadarao

Bradley Morgenfeld

Huaxiang Li

Christian J Ayala

Kripa Nidhan Chauhan

Hui Zang

Vibhor Jain

Haiting Wang

Elbert Emin Huang

Jinping Liu

Xusheng Kevin Wu

Haigou Huang

Hermann Wendt

Kaushik Arun Kumar

Guoxiang Ning

Scott Beasor

Louis DeWolf Lanzerotti

Matthew S Angyal

Habib Hichri

Atsushi Ogino

Catherine B Labelle

Vikrant Kumar Chauhan

Yuping Ren

Keith Donegan

Wan-jae Park

Anthony David Lisi

Qiang Fang

Haifeng Sheng

SherJang Singh

David Michael Permana

Mark Kelling

Oluwafemi O Ogunsola

Abdelsalam Aboketaf

Xiaohan Wang

Steven McDermott

Cheng Xu

Nicholas Robert Stokes

Tong Qing Chen

Muhammed Shafi Kurikka Valappil Pallachalil

Hideshi Miyajima

Dimitri R Kioussis

Joseph Edward Linville

Structures including an optical phase shifter and methods of forming a structure including an optical phase shifter. The structure comprises an optical phase shifter including a waveguide core having a first branch and a second branch laterally spaced from the first branch. The structure further comprises a thermoelectric device including a first plurality of pillars and a second plurality of pillars that alternate with the first plurality of pillars in a series circuit. The first plurality of pillars and the second plurality of pillars disposed adjacent to the first branch of the waveguide core, the first plurality of pillars comprises an n-type semiconductor material, and the second plurality of pillars comprises a p-type semiconductor material.

Optical phase shifter with one or more integrated thermoelectric devices

Structures and methods implement an enlarged multilayer nitride waveguide. The structure may include an inter-level dielectric (ILD) layer over a substrate. A first enlarged multilayer nitride waveguide is positioned in the ILD layer in a region of the substrate. A second multilayer nitride waveguide may also be provided in the ILD layer. A lower cladding layer defines a lower surface of the nitride waveguide(s). The lower cladding layer has a lower refractive index than the nitride waveguide(s). Additional lower refractive index cladding layers can be provided on the upper surface and/or sidewalls of the nitride waveguide(s). The enlarged nitride waveguide may be implemented with other conventional silicon and nitride waveguides.

Enlarged multilayer nitride waveguide for photonic integrated circuit

Methods of self-aligned multiple patterning. A hardmask is deposited over an interlayer dielectric layer. A mandrel is formed over the hardmask. A block mask is formed that covers a first lengthwise section of the mandrel and that exposes second and third lengthwise sections of the mandrel. After forming the block mask, the second and third lengthwise sections of the mandrel are removed to define a pattern including respective first and second mandrel lines that are separated from each other by the first lengthwise section of the mandrel. The first mandrel line and the second mandrel line expose respective portions of the hardmask, and the first lengthwise section of the mandrel line covers another portion of the hardmask. The pattern is transferred to the hardmask with an etching process, and subsequently transferred to the interlayer dielectric layer with another etching process.

Multiple patterning with mandrel cuts defined by block masks

The present disclosure relates to a structure which includes a first metal layer patterned as a mandrel, a dielectric spacer on the first metal layer, and a second metal layer on the dielectric spacer.

Metal on metal multiple patterning

In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.

Structure and method to improve overlay performance in semiconductor devices

This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap.

Integrated circuit structure to reduce soft-fail incidence and method of forming same

Methods of self-aligned multiple patterning. First and second mandrels are formed over a hardmask, and a conformal spacer layer is deposited over the first mandrel, the second mandrel, and the hardmask between the first mandrel and the second mandrel. A planarizing layer is patterned to form first and second trenches that expose first and second lengthwise portions of the conformal spacer layer respectively between the first and second mandrels. After patterning the planarizing layer, the first and second lengthwise portions of the conformal spacer layer are removed with an etching process to expose respective portions of the hardmask along a non-mandrel line. A third lengthwise portion of the conformal spacer layer is masked during the etching process by a portion of the planarizing layer and defines a non-mandrel etch mask.

Multiple patterning with lithographically-defined cuts

A method of fabricating interconnects in a semiconductor device is provided, which includes forming an interconnect layer having a conductive line and depositing a first aluminum-containing layer over the interconnect layer. A dielectric layer is deposited over the first aluminum-containing layer, followed by a second aluminum-containing layer deposited over the dielectric layer. A via opening is formed in the second aluminum-containing layer through to the conductive line, wherein the via opening has chamferless sidewalls.

Chamferless interconnect vias of semiconductor devices

The present disclosure generally relates to semiconductor structures and, more particularly, to smooth sidewall structures and methods of manufacture. The method includes: forming a plurality of mandrel structures; forming a first spacer material on each of the plurality of mandrel structures; forming a second spacer material over the first spacer material; and removing the first spacer material and the plurality of mandrel structures to form a sidewall structure having a sidewall smoothness greater than the plurality of mandrel structures.

Method of forming smooth sidewall structures using spacer materials

Methods of fabricating an interconnect structure. A hardmask is deposited over an interlayer dielectric layer, and a block mask is formed that covers an area on the hardmask. A sacrificial layer is formed over the block mask and the hardmask, and the sacrificial layer is patterned to form a mandrel that extends across the block mask.

Interconnects with variable space mandrel cuts formed by block patterning

Methods of lithographic patterning to form interconnect structures for a chip. A hardmask layer is formed on a dielectric layer. A sacrificial layer is formed on the hardmask layer. First opening and second openings are formed in the sacrificial layer that extend through the sacrificial layer to the hardmask layer. A resist layer is formed on the sacrificial layer. An opening is formed in the resist layer that is laterally located between the first opening in the first sacrificial layer and the second opening in the first sacrificial layer. The resist layer is comprised of a metal oxide resist material that is removable selective to the hardmask layer.

Lithographic patterning to form fine pitch features

Methods of lithographic patterning a dielectric layer. A first resist layer is formed on a hardmask layer, and a second resist layer is formed on the first resist layer. The second resist layer is patterned to form a first opening, which is transferred from the second resist layer to the first resist layer. The second resist layer is removed from the first resist layer after the first opening is transferred from the second resist layer to the first resist layer. The first resist layer is patterned to form a second opening laterally displaced in the first resist layer from the first opening. The first resist layer is comprised of a metal oxide photoresist that is removable selective to the hardmask layer. The hardmask layer and the dielectric layer may be subsequently patterned using first resist layer.

Dual photoresist approach to lithographic patterning for pitch reduction

A self-aligned double patterning (SADP) method is disclosed. The method may include forming a mandrel over an underlying layer, and undercutting the mandrel forming an undercut space under opposing sides of the mandrel. A pair of spacers may be formed adjacent the mandrel, each spacer including a vertical spacer portion on each side of the mandrel and an undercut spacer portion extending into the undercut space from the vertical spacer portion, the undercut spacer portions defining a sub-lithographic lateral dimension therebetween. The mandrels may be removed and, a sub-lithographic feature etched into at least the underlying layer using the spacers.

SADP method with mandrel undercut spacer portion for mandrel space dimension control

Growing community of inventors

Clifton Park, NY, United States of America

Ravi Prakash Srivastava