National Semiconductor Corporation

National Semiconductor Corportaion

Rashid Bashir

Francois Hebert

Datong Chen

Abul Ehsanul Kabir

Wipawan Yindeepol

Joel M McGregor

Paul McKay Moore

Kevin Carl Brown

Joseph Anthony DeSantis

Francois Herbert

Walkout in high voltage trench isolated semiconductor devices is inhibited by applying a voltage bias signal directly to epitaxial silicon surrounding the device. Voltage applied to the surrounding epitaxial silicon elevates the initial breakdown voltage of the device and eliminates walkout. This is because voltage applied to the surrounding epitaxial silicon reduces the strength of the electric field between the silicon of the device and the surrounding silicon. Specifically, application of a positive voltage bias signal to surrounding epitaxial silicon equal to or more positive than the most positive potential occurring at the collector during normal operation of the device ensures that no walkout will occur.

Elimination of walkout in high voltage trench isolated devices

Process for the formation of epitaxial layers with controlled n-type dopant concentration depth profiles for use in NPN bipolar transistors. The process includes first providing a semiconductor substrate (e.g. a &lsqb;100&rsqb;-oriented silicon wafer substrate) with an n-type collector precursor region formed on its surface, followed by forming an n-type (e.g. phosphorous or arsenic) in-situ doped epitaxial layer of a thickness t on the n-type collector precursor region. Next, an undoped epitaxial layer of a thickness t is formed on the n-type in-situ doped epitaxial layer. A p-type (e.g. boron) in-situ doped epitaxial base layer is subsequently formed on the undoped epitaxial layer. The process can also include the sequential formation of an undoped Si Ge epitaxial layer and a p-type in-situ doped Si Ge epitaxial layer between the undoped epitaxial layer and the p-type in-situ doped epitaxial base layer. Accumulation of the n-type dopant concentration in p-type epitaxial layers (such as the p-type in-situ doped epitaxial base layer or the p-type in-situ doped Si Ge epitaxial layer) that are formed subsequent to a non-p-type epitaxial layer (such as the undoped epitaxial layer or undoped Si Ge epitaxial layer, respectively) is controlled by manipulating the thickness ratio of t to t , while keeping the thickness of N-layer fixed at t (i.e. t &plus;t ).

Method for controlling an N-type dopant concentration depth profile in bipolar transistor epitaxial layers

A semiconductor device, polysilicon-contacted trench isolation structure that provides improved electrical isolation stability, a method of operating a polysilicon-contacted trench isolated semiconductor device, and a process for manufacturing a polysilicon-contacted trench isolation structure. The trench isolation structure includes an isolation trench formed in a semiconductor substrate. The isolation trench has a layer of trench lining oxide, a layer of trench lining silicon nitride and a trench fill polysilicon (poly 1) layer. Exposed lateral surfaces of the poly 1, which extend above the trench lining silicon nitride, are contacted to another layer of polysilicon (poly 2). The method of operation includes applying a bias voltage to the trench fill poly 1 layer via poly 2. The process for manufacture includes etching an isolation trench that extends through a layer of field oxide and into a semiconductor substrate. After forming layers of trench lining oxide, trench lining silicon nitride and trench fill poly 1 in the isolation trench, the trench lining silicon nitride is etched back to expose lateral surfaces of the trench fill poly 1. A poly 2 layer is then deposited and makes contact with the exposed lateral surfaces of the trench fill poly 1.

Semiconductor device trench isolation structure with polysilicon bias

A liquid crystal transducer pixel cell includes support pillars separating a top and bottom plate of the cell. During the process for forming the pixel cell, the support pillars are formed prior to formation of the pixel electrode. This process flow obviates the need for depositing a thick dielectric layer on top of the pixel electrode. This process flow also prevents exposure of the surface of the pixel electrode to etching during subsequent processing, preserving the reflectance of the pixel cell electrode. Finally, the process flow in accordance with the present invention eliminates the creation of keyhole voids within the support pillars by forming the support pillars over a flat upper level intermetal dielectric rather than over narrow trenches formed in the pixel electrode layer.

Thin liquid crystal transducer pixel cell having self-aligned support

A method of making a pressure sensor or acoustic transducer having high sensitivity and reduced size. A thin sensing diaphragm is produced by growing a single crystal, highly doped silicon layer on a substrate using a chemical vapor deposition process. The diaphragm is incorporated into a pressure sensor or acoustic transducer which detects pressure variations by a change in the capacitance of a capacitor which includes the diaphragm as a movable member. The thin diaphragm produces a highly sensitive device which can be fabricated in a smaller size than sensors or transducers having thicker diaphragms.

High sensitivity micro-machined pressure sensors and acoustic transducers

A semiconductor integrated circuit having a lateral bipolar transistor, is fabricated in a manner compatible with sub-micron CMOS processing. A base contact structure is formed over a bipolar active area, in essentially direct contact to a portion of the upper surface of the active region, essentially concurrent to the formation of a gate electrode on a gate dielectric layer in a CMOS active area. Sidewall spacers, adjacent the base contact region, are formed and a base region formed under the base contact structure using an oblique angle implantation. Emitter region and collector contact regions are formed concurrent with CMOS source and drain regions. An optional, oblique angle collector implant can be performed where desired.

Semiconductor integrated circuit having a lateral bipolar transistor

A method of manufacturing truly complementary bipolar transistors on a common substrate. The method results in the fabrication of vertical NPN and PNP transistors which have an identical structure and mode of operation, with both devices operating in the downward direction. The inventive method permits independent control of the characteristics of the two devices, producing a closely matched performance for both devices.

Complementary Si/SiGe heterojunction bipolar technology

A semiconductor device, polysilicon-contacted trench isolation- structure that provides improved electrical isolation stability, a method of operating a polysilicon-contacted trench isolated semiconductor device, and a process for manufacturing a polysilicon-contacted trench isolation structure. The trench isolation structure includes an isolation trench formed in a semiconductor substrate. The isolation trench has a layer of trench lining oxide, a layer of trench lining silicon nitride and a trench fill polysilicon (poly 1) layer. Exposed lateral surfaces of the poly 1, which extend above the trench lining silicon nitride, are contacted to another layer of polysilicon (poly 2). The method of operation includes applying a bias voltage to the trench fill poly 1 layer via poly 2. The process for manufacture includes etching an isolation trench that extends through a layer of field oxide and into a semiconductor substrate. After forming layers of trench lining oxide, trench lining silicon nitride and trench fill poly 1 in the isolation trench, the trench lining silicon nitride is etched back to expose lateral surfaces of the trench fill poly 1. A poly 2 layer is then deposited and makes contact with the exposed lateral surfaces of the trench fill poly 1.

Method of making high sensitivity micro-machined pressure sensors and

A process for anisotropically etching a tungsten silicide or tungsten polycide structure. If the silicide/polycide film has an overlying oxide layer, the insulating layer is removed by a gas mixture composed of CHF.sub.3 and C.sub.2 F.sub.6. The WSi.sub.x silicide layer is then etched in a reactive ion etch using a gas mixture formed from Cl.sub.2 and C.sub.2 F.sub.6, with sufficient O.sub.2 added to control polymer formation and prevent undercutting of the silicide. The polysilicon layer is then etched using a gas mixture formed from Cl.sub.2 and C.sub.2 F.sub.6. The result is a highly anisotropic etch process which preserves the critical dimension of the etched structures. The etch parameters may be varied to produce a tapered sidewall profile for use in the formation of butted contacts without the need for a contact mask.

Tungsten silicide/ tungsten polycide anisotropic dry etch process

A buried interconnect structure which is stable at the high temperatures involved in BiCMOS, bipolar, and CMOS transistor process flows, and a method of making the same. The interconnect structure is fully insulated and can be used to form stable, doped structures suitable for use as electrodes and gate structures in a CMOS process, or to form low resistance contacts to N or P-type silicon as part of a bipolar process. Because the interconnect structure is buried and fully insulated from surrounding structures, it may be used to form complex, multi-level devices having a minimized geometry and increased circuit density.

Method for forming buried interconnect structue having stability at high

A method of forming and planarizing a deep isolation trench in a silicon-on-insulator (SOI) structure begins with a base semiconductor substrate, a buried insulator layer formed on the base semiconductor substrate, and an active silicon layer formed on the buried insulator layer. First, an ONO layer is formed on the active silicon layer. The ONO layer includes a layer of field oxide, a first layer of silicon nitride and a layer of deposited hardmask oxide. A trench having sidewalls that extend to the buried oxide layer is formed. A layer of trench lining oxide is then formed on the exposed sidewalls of the trench. Then, a second layer of silicon nitride is conformally formed on the substrate. The second nitride layer is then anisotropically etched to remove the nitride from the exposed horizontal surface of the hardmask oxide and the buried oxide in the bottom of the trench, but leaving silicon nitride on the vertical sidewall portions of the hardmask oxide, on the sidewalls of the first nitride layer on the sidewalls of the field oxide and on the trench lining oxide. A layer of polysilicon is then deposited to fill the trench and etched back such that the top surface of the polysilicon substantially corresponds to the top surface of the layer of field oxide. The hardmask oxide layer is then removed and the top surface of the polysilicon layer is oxidized.

Method of forming and planarizing deep isolation trenches in a

A method of producing a high quality silicon surface prior to carrying out a selective epitaxial growth of silicon process for forming an active device region on a substrate. The process flow of the present invention eliminates the need for the sacrificial oxidation layer typically used in such processes. After the etching of a seed hole through the isolation oxide layer using a reactive ion etch a short, low power C.sub.2 F.sub.6 etch is performed. The present invention provides a simple and cost-effective way to eliminate reactive ion etch damage prior to SEG growth because the dry C.sub.2 F.sub.6 etch can be done in the same etch reactor in which the seed hole oxide etch is performed. In addition, the re-oxidation (sacrificial oxide) step is eliminated, reducing the number of process steps.

Method of producing high quality silicon surface for selective epitaxial

In a method of fabricating a self-aligned bipolar junction transistor with silicide extrinsic base contacts and selective epitaxial grown intrinsic base region, the sinker and buried N+ layer regions are formed in a semiconductor substrate with trench oxide isolation. Thin oxide is then formed on the structure. Next, metal silicide is deposited on the thin oxide and p-dopant implanted into the silicide. LTO is then deposited on the doped silicide followed by deposition of nitride. Next, the nitride, LTO and silicide layers are etched, stopping on the thin oxide layer. The thin oxide is then etched to expose the silicon. The etch undercuts the thin oxide under the nitride. A thin p+ epitaxial base is then selectively grown on the silicon and the metal silicide only. The base can be silicon or a silicon germanium layer to form a heterojunction transistor. Next, thin LTO is deposited followed by deposition of nitride. An RIE of the nitride is then performed to form nitride spacers, stopping on the thin LTO. The thin LTO is then wet etched to open the epitaxial base. A n-type, low-doped, selective single crystalline silicon emitter is then grown. This is followed by deposition of polysilicon and an n-dopant implant into the polysilicon. The polysilicon is then masked and etched to define a n+ polysilicon region in contact with the n-type single crystalline emitter. Next, a layer of oxide is deposited, followed by a furnace drive and rapid thermal anneal activation step for the base and emitter. Base, emitter and collector vias are opened and a metallization layer is formed and patterned to provide base, emitter and collector contacts.

Method for forming a self-aligned bipolar junction transistor with

A method of making a surface micro-machined accelerometer using a silicon-on-insulator (SOI) wafer structure. Both the acceleration (or deceleration) sensor and associated signal conditioning circuitry are monolithically fabricated on the same substrate. The top silicon layer of the SOI wafer is used as the sensing member, corresponding to the movable, common electrode of a differential capacitor pair. The components of the signal conditioning circuitry are fabricated in the SOI layer using standard SOI processing techniques. Because the top silicon layer is single crystal silicon, it does not suffer from the stress related warping common with polysilicon members. In addition, because the method described is compatible with bipolar, BiCMOS, or CMOS process flows, it may be used to fabricate faster and lower noise level signal conditioning circuitry than can be obtained using current techniques for making monolithic accelerometers.

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Santa Clara, CA, United States of America

Rashid Bashir