Average Co-Inventor Count = 3.68
ph-index = 4
The patent ph-index is calculated by counting the number of publications for which an author has been cited by other authors at least that same number of times.
Company Filing History:
1. Micron Technology Incorporated (13 from 38,002 patents)
13 patents:
1. 9741580 - Substrate mask patterns, methods of forming a structure on a substrate, methods of forming a square lattice pattern from an oblique lattice pattern, and methods of forming a pattern on a substrate
2. 9583381 - Methods for forming semiconductor devices and semiconductor device structures
3. 9460998 - Semiconductor constructions and methods of forming semiconductor constructions
4. 9229328 - Methods of forming semiconductor device structures, and related semiconductor device structures
5. 8999852 - Substrate mask patterns, methods of forming a structure on a substrate, methods of forming a square lattice pattern from an oblique lattice pattern, and methods of forming a pattern on a substrate
6. 8937018 - Methods of forming a pattern on a substrate
7. 8889559 - Methods of forming a pattern on a substrate
8. 8889558 - Methods of forming a pattern on a substrate
9. 8796086 - Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate
10. 8741781 - Methods of forming semiconductor constructions
11. 8586429 - Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate
12. 8389353 - Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate
13. 8039340 - Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate