International Business Machines Corporation

Other

Rangarajan Jagannathan

David Lee Rath

Harald F Okorn-Schmidt

Kenneth John McCullough

Keith Randal Pope

Karen P Madden

Mahadevaiyer Krishnan

Judson Robert Holt

Glenn Walton Gale

Donald Francis Canaperi

Gregory P Wandy

Kevin K Chan

Richard Stephan Wise

Emanuel Israel Cooper

John Christopher Arnold

Wesley Charles Natzle

Huajie Chen

Ashima B Chakravarti

Stefan Schmitz

Randolph F Knarr

Sadanand Vinayak Deshpande

Michael Ray Sievers

Scott Alan Estes

Xuefeng Hua

Bruce Bennett Doris

Ying Di Zhang

Sampath Purushothaman

Tze-Chiang Chen

Max Gerald Levy

Hongwen Yan

Sean R Kirkpatrick

Cuc Kim Huynh

Matthew J Sendelbach

Clifford Owen Morgan, Iii

William C Wille

Qingyun Yang

James Anthony Tornello

Terrance M Wright

Donald J Delehanty

Thomas Edwin Sandwick

Thomas J Martin

Frank J Schmidt, Jr

George F Ouimet, Jr

Bryan N Rhoads

Donna Diane Miura

Scott A Sikorski

Uma Satyendra

Amarnath Jha

A method of processing a trench, via, hole, recess, void, or other feature that extends a depth into a substrate to a base or bottom and has an opening by irradiation with an accelerated neutral beam derived from an accelerated gas cluster ion beam for processing materials at the base or bottom of the opening.

Method and apparatus for neutral beam processing based on gas cluster ion beam technology

In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.

Transistor devices and methods of making

Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and the recesses are filled by epitaxial deposition. The epi can be in-situ doped or subsequently implanted to form source/drain extensions. Alternatively, the etch is immediately followed by the COR pre-clean, which is followed by epitaxial deposition to fill the recesses. During the epitaxial deposition process, the deposited material is doped to form in-situ doped halos and, then, the dopant is switched to form in-situ doped source/drain extensions adjacent to the halos. Alternatively, after the in-situ doped halos are formed the deposition process is performed without dopants and an implant is used to form source/drain extensions.

Metal oxide field effect transistor with a sharp halo

Adding at least one non-silicon precursor (such as a germanium precursor, a carbon precursor, etc.) during formation of a silicon nitride, silicon oxide, silicon oxynitride or silicon carbide film improves the deposition rate and/or makes possible tuning of properties of the film, such as tuning of the stress of the film. Also, in a doped silicon oxide or doped silicon nitride or other doped structure, the presence of the dopant may be used for measuring a signal associated with the dopant, as an etch-stop or otherwise for achieving control during etching.

Method for producing a doped nitride film, doped oxide film and other doped films

Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite differences in the composition of the gate stack and resulting differences in the etch rates. A thin polysilicon layer is used for one type of gate electrodes and a silicon-containing layer are used for the other type of gate electrodes in these integration schemes to balance the different etch rates and to enable etching of the two different gate stacks.

Integration schemes for fabricating polysilicon gate MOSFET and high-K dielectric metal gate MOSFET

Metal oxide field effect transistor with a sharp halo and a method of forming the transistor

Doped nitride film, doped oxide film and other doped films

Method for planarizing photoresist

A silicate glass is selectively etched employing a composition containing a fluoride containing compound and certain organic solvents. Preferred compositions also include water.

Selective etching of silicate

Oxides such as those commonly used in interlevel dielectrics may be removed employing a liquid composition containing a fluoride-containing compound and an organic solvent. Preferred compositions are substantially nonaqueous and include an anhydride. Improved methods for selective removal of oxides, especially for removal of silicon oxides where pre-exposed (or conductive metal - containing) features are present, where metal (conductive metal - contaimg) features are to be exposed by the desired oxide removal, or where the silcon oxide otherwise contacts metal (or conductive metal - containing) features are provided.

Removal of dielectric oxides

A method is provided for treating a plurality of semiconductor substrates using the same aqueous SC-1 solution which solution removes and/or inhibits contamination of the semiconductor surfaces by metallic ions present in the solution or on the substrate surface comprising a basic solution containing hydrogen peroxide and an oxidation-resistant chelating additive such as CDTA in an amount effective to provide the desired treatment results. The SC-1 solution may be the conventional 5:1:1 (water:NH,OH:H,O,) solution or a dilute solution such as a 5:x:1 to 200:x:l solution wherein x is 0.025 to 2.

Method for cleaning semiconductor devices

Etching residue is selectively removed employing a substantially non-aqueous composition containing a fluoride containing compound and certain organic solvents. Preferred compositions also include an anhydride.

Selective removal of etching residues

Silicon oxide is removed from an article employing a liquid composition containing a fluoride-containing compound, organic solvent, and water. The methods of the invention are especially useful for removal of silicon oxide formed by thermal oxidation of a silicon substrate.

Removal of silicon oxide

A colloidal silica slurry containing triethanolamine is used in a chemical mechanical polishing process to polish multiple material substrates, such as silicon wafers containing silicon oxide where a thin underlayer of silicon nitride is used as a stop layer. The colloidal silica slurry containing triethanolamine is capable of achieving an oxide to nitride selectivity during polishing up to a demonstrated ratio of 28:1.

Chemical mechanical polishing of multiple material substrates and slurry

Growing community of inventors

Hopewell Junction, NY, United States of America

Rangarajan Jagannathan