International Business Machines Corporation

Samsung Electronics Co., Ltd.

Infineon Technologies Ag

Randy William Mann

Jed Hickory Rankin

Jeffrey Scott Brown

Edward J Nowak

Robert J Gauthier, Jr

Steven H Voldman

Katherine Lynn Saenger

James William Adkisson

Alfred Grill

Andres Bryant

Wilbur David Pricer

Thomas M Shaw

Deborah A Neumayer

Charles Thomas Black

Werner A Rausch

Francis Roger White

Subhash Balakrishna Kulkarni

Chung H Lam

Terence B Hook

Matthew Joseph Breitwisch

Wayne Frederick Ellis

James Spiros Nakos

Jerome Brett Lasky

James Allan Bruce

Lawrence Alfred Clevenger

Brent A Anderson

Ramachandra Divakaruni

Qizhi Liu

Cyril Cabral, Jr

Kirk David Peterson

Marwan H Khater

Stephen Victor Kosonocky

Robert C Wong

William Joseph Murphy

Paul Christian Parries

Andreas Daniel Stricker

Luigi Ternullo, Jr

Jonathan Daniel Chapple-Sokol

Robert J Purtell

Peter John Geiss

Eric Adler

Glen L Miles

Jeffery Howard Oppold

Jae-Sung Rieh

Jeffrey H Oppold

Archibald John Allen

Francois M d'Heurle

David J Wager

Anthony K Stamper

Jeffrey P Gambino

John Edward Cronin

David V Horak

Charles W Koburger, Iii

John Joseph Pekarik

Bomy A Chen

James Albert Slinkman

Norman Jay Rohrer

Christopher Stephen Putnam

K Paul Muller

David Michael Fried

Fariborz Assaderaghi

Paul David Kartschoke

James M Harper

Ronnen Andrew Roy

Gregory Costrini

Carter W Kaanta

William A Klaasen

BethAnn Rainey

Daniel Scott Vanslette

Peter Edwin Cottrell

Michael James Lercel

Andrew J Watts

John R Abernathey

Xavier Baie

William R Tonti

John J Ellis-Monaghan

John Atkinson Fifield

Kerry Bernstein

Subramanian Srikanteswara Iyer

Herbert Lei Ho

John Edward Barth, Jr

Alain F Loiseau

Johnathan E Faltermeier

Minh H Tong

Thomas George Ference

Edward W Conrad

Deok-kee Kim

Oliver Desmond Patterson

Jae-Eun Park

John Anthony Bracchitta

Dale Warner Martin

Richard Andre Wachnik

Jason Paul Gill

James McKell Edwin Harper

Daniel C Cole

Kurt R Kimmel

Paul William Pastel

Beth Ann Rainey

Edward W Sengle

Donald Walter Rakowski

Methods of forming an electrically conductive path under a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate and an integrated circuit including the path are disclosed. In one embodiment, the method includes forming an electrically conductive path below a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate, the method comprising: forming a first barrier oxide layer on a semiconductor substrate; forming the electrically conductive path within the first barrier oxide layer; and forming a second barrier oxide layer on the first barrier oxide layer. The electrically conductive path allows reduction of SRAM area by forming a wiring path underneath the barrier oxide layer on the SOI substrate.

Electrically conductive path forming below barrier oxide layer and integrated circuit

A design process includes inputting a design file representing a circuit design embodied in a non-transitory computer-readable medium, and using a computer to translate the circuit design into a netlist. The netlist comprises a representation of a plurality of wires, transistors, and logic gates, and is stored in the non-transitory computer-readable medium. When executed by the computer, the netlist produces the circuit design. The circuit design comprises a static random access memory ('SRAM') including a plurality of SRAM cells arranged in an array, including a plurality of rows and a plurality of columns, and a plurality of column voltage control circuits corresponding to respective ones of the plurality of columns of the array. Each of the plurality of voltage control circuits is coupled to an output of a power supply and is operable to temporarily reduce a voltage upon arrival of a bit select signal provided to power supply inputs of a plurality of SRAM cells belonging to a selected column of the plurality of columns. The selected column is selected during a write operation in which a bit is written to one of the plurality of SRAM cells belonging to the selected column. Each column voltage control circuit includes an NFET and a pair of PFETs. Each NFET and pair of PFETs has a conduction path directly connected between the output of the power supply and the power supply inputs of the plurality of SRAM cells.

Circuit design

An array of deep trenches is formed in a doped portion of the semiconductor substrate, which forms a lower electrode. A dielectric layer is formed on the sidewalls of the array of deep trenches. The array of deep trenches is filled with a doped semiconductor material to form an upper electrode comprising a top plate portion and a plurality of extension portions into the array of trenches. In a depletion mode, the bias condition across the dielectric layer depletes majority carriers within the top electrode, thus providing a low capacitance. In an accumulation mode, the bias condition attracts majority carriers toward the dielectric layer, providing a high capacitance. Thus, the trench metal-oxide-semiconductor (MOS) varactor provides a variable capacitance depending on the polarity of the bias.

Highly tunable metal-on-semiconductor trench varactor

A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Flip FERAM cell and method to form same

Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.

Methods of base formation in a BiCOMS process

Semiconductor integrated test structures are designed for electron beam inspection of semiconductor wafers. The test structures include pattern features that are formed in designated test regions of the wafer concurrently with pattern features of integrated circuits formed on the wafer. The test structures include conductive structures that are designed to enable differential charging between defective and non-defective features (or defective and non-defection portions of a given feature) to facilitate voltage contrast defect detection of CMOS devices, for example, using a single, low energy electron beam scan, notwithstanding the existence of p/n junctions in the wafer substrate or other elements/features.

Semiconductor integrated test structures for electron beam inspection of semiconductor wafers

A static random access memory ('SRAM') is provided which includes a plurality of SRAM cells arranged in an array having a plurality of portions. The SRAM includes a plurality of voltage control circuits corresponding to respective ones of the plurality of portions of the array. Each of the plurality of voltage control circuits is coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected one of the plurality of portions of the SRAM. The power supply voltage to the selected portion is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected portion.

SRAM voltage control for improved operational margins

Methods of base formation in a BiCMOS process

A static random access memory ('SRAM') is provided which includes a plurality of SRAM cells arranged in an array. The array includes a plurality of rows and a plurality of columns. The SRAM includes a plurality of voltage control corresponding to respective ones of the plurality of columns of the array. Each of the plurality of voltage control circuits are coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected column of columns of the SRAM. The selected column is selected and the power supply voltage to that column is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected column.

A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design.

Low-cost deep trench decoupling capacitor device and process of manufacture

The present invention provides a method of forming an ultra-thin and uniform layer of Si including the steps of providing a substrate having semiconducting regions separated by insulating regions; implanting dopants into the substrate to provide an etch differential doped portion in the semiconducting regions underlying an upper Si-containing surface of the semiconducting regions; forming a trench in the substrate including the semiconducting regions and the insulating regions; removing the etch differential doped portion from the semiconductor regions to produce a cavity underlying the upper surface of the semiconducting regions; and filling the trench with a trench dielectric, wherein the trench dielectric material encloses the cavity underlying the upper Si-containing surface of the semiconducting regions. The upper Si-containing surface of the semiconducting regions has a uniform thickness of less than about 100 &#x212b;.

Isolated fully depleted silicon-on-insulator regions by selective etch

Growing community of inventors

Jericho, VT, United States of America

Randy William Mann