Globalfoundries Inc.

University of Virginia

Globalfoundries U.S. Inc.

Randy W Mann

Bipul C Paul

William McMahon

Hui Zang

Akhilesh Gautam

Yoann Mamy Randriamihaja

Yuncheng Song

Anurag Mittal

Ratheesh Ramachandran Thankalekshmi

Sonia Ghosh

Ruilong Xie

Julien Frougier

Xusheng Kevin Wu

Scott D Luning

Benton H Calhoun

Kingsuk Maitra

Norman Chen

Xiaoqiang Zhang

Shaowen Gao

Hong Yu

Yi Qi

Guoxiang Ning

Jerome Ciavatti

Bingwu Liu

Yanping Shen

Hsien-Ching Lo

Guowei Xu

Wei Hong

Hongliang Shen

Suresh Uppal

Jae Gon Lee

Yongjun Shi

Meixiong Zhao

Sanjay Parihar

Anuj Gupta

Sriram Balasubramanian

Anton Tokranov

Sangmoon J Kim

Sandeep Puri

Vivek Joshi

Richard Francis

Structures and static random access memory bit cells including complementary field effect transistors and methods of forming such structures and bit cells. A first complementary field-effect transistor has a first storage nanosheet transistor, a second storage nanosheet transistor stacked over the first storage nanosheet transistor, and a first gate electrode shared by the first storage nanosheet transistor and the second storage nanosheet transistor. A second complementary field-effect transistor has a third storage nanosheet transistor, a fourth storage nanosheet transistor stacked over the third storage nanosheet transistor, and a second gate electrode shared by the third storage nanosheet transistor and the fourth storage nanosheet transistor. The first gate electrode and the second gate electrode are arranged in a spaced arrangement along a longitudinal axis. All gate electrodes of the SRAM bitcell may be arranged in a 1CPP layout.

Structures and SRAM bit cells integrating complementary field-effect transistors

Structures including static random access memory bit cells and methods of forming a structure including static random access memory bit cells. A first bit cell includes a first plurality of semiconductor fins, and a second bit cell includes a second plurality of semiconductor fins. A deep trench isolation region is laterally positioned between the first plurality of semiconductor fins of the first bit cell and the second plurality of semiconductor fins of the second bit cell.

SRAM bit cells formed with dummy structures

Structures for a static random access memory (SRAM) bitcell and methods for forming a SRAM bitcell. The SRAM includes a storage element with a first pull-up (PU) vertical-transport field-effect transistor (VTFET) having a first bottom source/drain region and a fin projecting from the first bottom source/drain region, and a second pull-up (PU) VTFET with a second bottom source/drain region and a fin projecting from the second bottom source/drain region. The fin of the first PU VTFET is arranged over a first active region in which the first bottom source/drain region is centrally arranged, and the fin of the second PU VTFET is arranged over a second active region in which the second bottom source/drain region is centrally arranged. The second source/drain region is aligned with the first bottom source/drain region. A read port may be connected with the storage element, and may also be formed using VTFETs.

Static random access memory cells with arranged vertical-transport field-effect transistors

The present disclosure relates to semiconductor structures and, more particularly, to a SRAM structure with alternate gate pitches and methods of manufacture. The structure includes an array of memory cells having a plurality of gate structures with varying gate pitches, the varying gate pitches comprising a first dimension sized for placement of a bitline contact and a second dimension sized for placement of source/drain contacts, the first dimension being larger than the second dimension.

SRAM structure with alternate gate pitches

A first S/D region includes a first P-type region, a first N-type region, and a first conductive layer thereon to define a first cell node. A second S/D region includes a second P-type region, a second N-type region, and a second conductive layer thereon to define a second cell node. A PDL transistor and PGLA, PGLB transistors have bottom SD regions in the first N-type region. A PUL transistor has a bottom SD region positioned in the first P-type region. A PDR transistor and PGRA, PGRB have bottom SD regions in the second N-type region. A PUR transistor has a bottom SD region in the second P-type region. A first gate is positioned around channel regions of the PUL and PDL transistors and conductively coupled to the second node. A second gate is positioned around channel regions of the PUR and PDR transistors and conductively coupled to the first node.

Dual port vertical transistor memory cell

One illustrative 6T SRAM cell structure disclosed herein includes a first active region with a first N-type pass gate transistor, a first N-type pull-down transistor and a first P-type pull-up transistor, each of which are formed in and above the first active region, wherein the first N-type pull-down transistor is positioned laterally between the first N-type pass gate transistor and the first P-type pull-up transistor, and a second active region with a second N-type pass gate transistor, a second N-type pull-down transistor and a second P-type pull-up transistor, each of which are formed in and above the second active region, wherein the second N-type pull-down transistor is positioned laterally between the second N-type pass gate transistor and the second P-type pull-up transistor.

Six-transistor (6T) SRAM cell structure

Various aspects include a static random access memory (SRAM) bitcell array structure. In some cases, the SRAM bitcell array structure includes at least one fin in an array of fins in a substrate, where a width of a first portion of the at least one fin is less than a width of a second portion of the at least one fin in the array of fins.

Method of reducing fin width in FinFet SRAM array to mitigate low voltage strap bit fails

A method of reducing fin width in an integrated circuit (IC) including oxidizing an exposed portion of at least one fin in an array of fins resulting in a reduction in the width of the exposed portion of the at least one fin. A first hard mask may be located over the array of fins except the exposed portion of the at least one fin during oxidation. A second hard mask may be optionally located over the array of fins, under the first hard mask, and covering a portion of the exposed portion of the at least one fin during the oxidizing of the exposed portion of the at least one fin. The oxidizing the exposed portion of the at least one fin may occur before forming a shallow trench isolation (STI) between pairs of fins in the array of fins, after forming the STI between the pairs of fins in the array of fins, and/or after removing a dummy gate during a replacement metal gate process.

Method of reducing fin width in FinFET SRAM array to mitigate low voltage strap bit fails

The disclosure provides integrated circuit (IC) structure including: a substrate; a shallow trench isolation (STI) positioned between the first and second regions of the substrate; a first transistor with a channel region is positioned on the first region of the substrate, and spacer positioned on the first region of the substrate and the STI; and a gate metal positioned on the spacer. The gate metal includes a gate contact region positioned over the first source/drain region of the substrate, and surrounding the channel region. Across-couple region extends laterally from the gate contact region to the source/drain region of a second transistor formed on the second region of the substrate.

Cross couple structure for vertical transistors

Disclosed is a method of forming an integrated circuit (IC) structure with multiple non-planar transistors having different effective channel widths. In the method, sacrificial gates are removed from partially completed transistors, creating gate openings that expose sections of semiconductor fins between source/drain regions. Prior to forming replacement metal gates in the gate openings, additional process steps are performed so that, in the resulting IC structure, some transistors have different channel region heights and, thereby different effective channel widths, than others. These steps can include forming isolation regions in the bottoms of some gate openings. Additionally or alternatively, these steps can include filling some gate openings with a sacrificial material, recessing the sacrificial material to expose fin tops within those gate openings, either recessing the fin tops or forming isolation regions in the fin tops, and removing the sacrificial material. Also disclosed is an IC structure formed according to the method.

Integrated circuit structure incorporating non-planar field effect transistors with different channel region heights and method

We disclose methods, apparatus, and systems for improving semiconductor device writeability through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS through the array VCS driver.

Methods, apparatus, and system for global healing of write-limited die through bias temperature instability

Method, apparatus, and system for improving semiconductor device writeability at row/bit level through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS, wherein the first array supply voltage and the second array supply voltage are greater than the operational array supply voltage. By virtue of BTI, application of the first array supply voltage may lead to improved writeability of one or more cells of the device.

Method, apparatus, and system for targeted healing of write fails through bias temperature instability

Approaches for providing a hardmask used during a halo/extension implant of a static random access memory (SRAM) layout for a semiconductor device are disclosed. Specifically, approaches are provided for forming a pull-down (PD) transistor over a substrate; forming a pass-gate (PG) transistor over the substrate; and patterning a hardmask over the device, the hardmask including a first section adjacent the PD transistor and a second section adjacent the PG transistor, wherein a distance between the first section and the PD transistor is shorter than a distance between the second section and the PG transistor. The respective distances between the first section and the PD transistor, and the second section and the PG transistor, are selected to prevent a halo/extension implant from impacting one side of the PD transistor, while allowing the halo/extension implant to impact both sides of the PG transistor.

Hardmask for a halo/extension implant of a static random access memory (SRAM) layout

Method, apparatus, and system for global healing of write-limited die through bias temperature instability

Growing community of inventors

Milton, NY, United States of America

Randy W Mann