Intel Corporation

Micron Technology Incorporated

Randy J Koval

Hiroyuki Sanda

John David Hopkins

Gordon A Haller

Hongbin Zhu

Jie Sun

Zhenyu Lu

Fatma Arzum Simsek-Ege

Krishna Kumar Parat

Ronald Allen Weimer

Thomas M Graettinger

Max F Hineman

Alex J Schrinsky

Christopher J Larsen

Vinayak Shamanna

Srikant Jayanti

Meng-Wei Kuo

William R Kueber

Srivardhan Gowda

Henok T Mebrahtu

Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. A select device can be coupled to one end of the plurality of memory cells and at least partially surround the pillar. An asymmetric assist device can be coupled between the select device and one of a source connection or a drain connection. The asymmetric assist device can have a portion that at least partially surrounds the pillar and another portion that at least partially surrounds the source or drain connection.

Methods and apparatuses including an asymmetric assist device

Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

Semiconductor devices and methods of fabrication

Storage node configurations are described. A storage node (e.g., a floating gate or a charge trap layer of a three-dimensional (3D) NAND flash device) include a channel-facing surface with a radius of curvature. For example, a channel-facing surface of the storage node may be concave. A control gate-facing surface of the storage node may instead, or additionally, also include a radius of curvature. The radius of curvature of the channel-facing and/or control gate-facing surfaces of the storage node is less than or equal to the radius of the channel layer.

Non-volatile memory with storage nodes having a radius of curvature

A 3D memory structure including a modified floating gate and dielectric layer geometry is described. In embodiments, a memory cell includes a channel region and a floating gate where a length of the floating gate along a direction of the channel region is substantially longer than a length of the floating gate along an orthogonal direction along the channel region. A control gate adjacent to the floating gate extends at least as long as the control gate along the direction of the channel region and includes a tapered edge extending away from the channel region towards the control gate. In embodiments, a dielectric layer between the control gate and the floating gate may follow the tapered edge along the floating gate and form a discrete region proximate to the floating gate to at least partially insulate the floating gate from an adjacent memory cell. Other embodiments are disclosed and claimed.

Modified floating gate and dielectric layer geometry in 3D memory arrays

An apparatus is described having a memory. The memory includes a vertical stack of storage cells, where, a first storage node at a lower layer of the vertical stack has a different structural design than a second storage node at a higher layer of the vertical stack.

Vertical memory having varying storage cell design through the storage cell stack

An embodiment of a method of forming a portion of a memory array includes forming a conductor with a concentration of germanium that decreases with an increasing thickness of the conductor, removing a portion of the conductor at a rate governed by the concentration of germanium to form a tapered first opening through the conductor, removing a sacrificial material below the conductor to form a second opening contiguous with the tapered first opening, and forming a semiconductor in the contiguous first and second openings, wherein a portion of the semiconductor pinches off within the first opening adjacent an upper surface of the conductor before the contiguous first and second openings are completely filled with the semiconductor.

Methods of forming a portion of a memory array having a conductor having a variable concentration of germanium

A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. The memory device utilizes a local buried channel dielectric in a NAND string that reduces bulk channel leakage at the edge of the NAND string where the electric field gradient along the direction of the string pillar is at or near a maximum during programming operations. The memory device comprises a channel that is coupled at one end to a bitline and at the other end to a source. A select gate is formed at the end of the channel coupled to the bitline to selectively control conduction between the bitline and the channel. At least one non-volatile memory cell is formed along the length of the channel between the select gate and the second end of the channel. A local dielectric region is formed within the channel at the first end of the channel.

Local buried channel dielectric for vertical NAND performance enhancement and vertical scaling

Methods for building a memory device or electronic system may include a memory cell body extending from a substrate, a self-aligned floating gate separated from the memory cell body by a tunneling dielectric film, and a control gate separated from the self-aligned floating gate by a blocking dielectric film. The floating gate is flanked by the memory cell body and the control gate to form a memory cell, and the self-aligned floating gate is at least as thick as the control gate.

Self-aligned floating gate in a vertical memory structure

An embodiment of a method of forming a control gate includes forming a conductor having a concentration of germanium that varies with a thickness of the conductor, and removing portions of the conductor at a variable rate that is governed, at least in part, by the concentration of the germanium.

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Boise, ID, United States of America

Randy J Koval