Intel Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Mitsubishi Electric Information Technology Center America, Inc.

Terarecon, Inc.

Mitsubishi Electric Information Technology Center America, Inc (ita)

Intel Corporatioon

Randy B Osborne

Hugh C Lauer

Chung-Te Lin

Hanspeter Pfister

Min Cao

Hemant G Rotithor

Sheng-Chih Lai

Jasmin Ajanovic

Stanley Steve Kulick

Kuljit Singh Bains

Yu-Der Chih

Thomas P Thomas

Nagi Aboulenein

Hsueh-Chih Yang

John H Howard

Win San Khwa

David J Harriman

John B Halbert

James A McCall

Hiroki Noguchi

Christopher P Mozak

James E Akiyama

Zvika Greenfield

William H Clifford

Qin Zheng

Philip Abraham

Erik W Peter

Kumar K Chinnaswamy

Michael Gutzmann

Mauro Cocco

Alessandro Paschina

Shelley Chen

Johanna M Swan

Adel A Elsherbini

Van H Le

Aleksandar Aleksov

Shawna M Liff

Feras Eid

Katherine H Chiang

Stephen H Gunther

Zohar Bogin

Joseph A Bennett

Rajesh Kumar

Kenneth C Creta

Julien Sebot

Nadav Bonen

Daniel Greenspan

Chia Shen

Abhishek Singhal

Israel Diamand

Asaf Rubinstein

James M Knittel

Ram Huggahalli

Raul N Gutierrez

Ingmar Bitter

Donald W McCauley

Erin D Francom

Ken M Crocker

Ross T Casley

Abhijit Ghosh

Somvir Singh Dahiya

Joshua Een

Buderya S Acharya

Surya Kareenahalli

Douglas J Hahn

Harufusa Kondoh

Scot Kellar

Greg Lemos

Kevin Xiaoqiang Zhang

Vamsee K Madavarapu

William Clifford

Various embodiments of the present application are directed towards a bipolar selector having independently tunable threshold voltages, as well as a memory cell comprising the bipolar selector and a memory array comprising the memory cell. In some embodiments, the bipolar selector comprises a first unipolar selector and a second unipolar selector. The first and second unipolar selectors are electrically coupled in parallel with opposite orientations and may, for example, be diodes or some other suitable unipolar selectors. By placing the first and second unipolar selectors in parallel with opposite orientations, the first unipolar selector independently defines a first threshold voltage of the bipolar selector and the second unipolar selector independently defines a second threshold voltage of the bipolar selector. As a result, the first and second threshold voltages can be independently tuned by adjusting parameters of the first and second unipolar selectors.

Bipolar selector with independently tunable threshold voltages

A thermal management scheme, for a multichip module, that is aware of various dies in a stack (horizontal and/or vertical) and heat generated from them, local hot spots in a victim die, and hot spots in aggressor die(s). Each victim die receives telemetry information from thermal sensors located in aggressor dies as well as local thermal sensors in the victim die. The telemetry information is used to enable a virtual sensing scheme where temperature for a target die (e.g., a victim die) and/or its intellectual property (IP) domain is estimated or calculated. The estimated or calculated temperature is then used for performance management of the victim and/or aggressor dies in the stack.

Thermal management in horizontally or vertically stacked dies

A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.

Memory error detection and correction

Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include an interposer, including an organic dielectric material, and a microelectronic component coupled to the interposer by direct bonding.

Direct bonding in microelectronic assemblies

In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit includes a first memory device and a second memory device arranged over a substrate. The first memory device is coupled to a first bit-line. The second memory device is coupled to a second bit-line. A shared control element is arranged within the substrate and is configured to provide access to the first memory device and to separately provide access to the second memory device. The shared control element includes one or more control devices sharing one or more components.

Interleaved routing for MRAM cell selection

A memory cell includes a memory cell stack, a first word line, a second word line, a bit line coupled to one end of the memory cell stack, a first unidirectional selector having one end coupled to another end of the memory cell stack and another end coupled to the first word line, and a second unidirectional selector having one end coupled to the another end of the memory cell stack and another end coupled to the second word line. Current flow directions of the first unidirectional selector and the second unidirectional selector are opposite to each other.

Random access memory

A system for automatic hardware ZLW insertion for IPU image streams is described herein. The system includes a memory and a processor. The memory is to store imaging data. The processor is coupled to the memory. The processor is to receive an image stream request and determine a data transfer type. The processor is also to insert a zero length write (ZLW) instruction ahead of the image stream request in response to the image stream request beginning on a different page when compared to the current page in a page history. Additionally, the processor is to insert a ZLW instruction ahead of the image stream request in response to the image stream request crossing a page boundary.

Automatic hardware ZLW insertion for IPU image streams

Described herein are embodiments of asymmetric memory management to enable high bandwidth accesses. In embodiments, a high bandwidth cache or high bandwidth region can be synthesized using the bandwidth capabilities of more than one memory source. In one embodiment, memory management circuitry includes input/output (I/O) circuitry coupled with a first memory and a second memory. The I/O circuitry is to receive memory access requests. The memory management circuitry also includes logic to determine if the memory access requests are for data in a first region of system memory or a second region of system memory, and in response to a determination that one of the memory access requests is to the first region and a second of the memory access requests is to the second region, access data in the first region from the cache of the first memory and concurrently access data in the second region from the second memory.

Concurrent accesses of asymmetrical memory sources

An electronic processing system may include a processor and a multi-level memory coupled to the processor, the multi-level memory including at least a main memory and a fast memory, the fast memory having relatively faster performance as compared to the main memory. The system may further include a fast memory controller coupled to the fast memory and a graphics controller coupled to the fast memory controller. The fast memory may include a cache portion allocated to a cache region to allow a corresponding mapping of elements of the main memory in the cache region, and a graphics portion allocated to a graphics region for the graphics controller with no corresponding mapping of the graphics region with the main memory.

Operating system transparent system memory abandonment

Methods and apparatuses for providing a hybrid memory module having both volatile and non-volatile memories to replace a DDR channel in a processing system.

Hybrid memory architectures

Growing community of inventors

Newton, MA, United States of America

Randy B Osborne