Delco Electronics Corporation

Gm Global Technolgoy Operations, Inc.

Randy A Rusch

John Robert Schlais

John R Schlais

Thomas H Simacek

David E Moss

Richard A Summe

Douglas R Schnabel

Stephen L Inman

Jack D Parrish

Karl Edward Stone

Robert J Heideman

Michael S Baird

Charles A Bright, Jr

Douglas A Kittle

Bernhard G Ulfers

A method of making an EPROM transistor in a high density CMOS integrated circuit having a substrate to gate electrode material capacitor. The EPROM transistor is made using only the steps used to make the other components of the high density CMOS integrated circuit. The EPROM transistor is programmable at low voltages which high density CMOS transistors can handle.

EPROM in high density CMOS having added substrate diffusion

A method of making an EPROM transistor in a high density CMOS integrated circuit having a gate electrode to metallization capacitor. The EPROM transistor is made using only the steps used to make the other components of the high density CMOS integrated circuit. The EPROM transistor is programmable at low voltages which high density CMOS transistors can handle.

Method of making EPROM in high density CMOS having metallization

A method of making an EPROM transistor in a high density CMOS integrated circuit having a poly to poly capacitor and including two layers of polysilicon. The EPROM transistor is made using only the steps used to make the other components of the high density CMOS integrated circuit. The EPROM transistor is programmable at the low voltages which high density CMOS transistors can handle.

EPROM in double poly high density CMOS

A semiconductor device aluminum-containing metallization system that is particularly useful for integrated circuits (ICs) having P-type contact regions and also having a likelihood of extended exposure to elevated temperatures. Use of an aluminum/silicon diffusion barrier formed of an amorphous tungsten/silicon on such ICs is made commercially practical. A titanium or transition metal silicide layer is disposed beneath the amorphous tungsten/silicon layer, to consistently provide durable low resistance electrical contacts to P-type regions of the IC.

Multilayer metallization for silicon semiconductor devices including a

A process for fabricating a high voltage CMOS transistor having a non-self aligned implanted channel which permits the operation of the device at high voltages. The non-self aligned implanted channel does not require alignment with the gate electrode of the CMOS device, but is accurately implanted early in the fabrication of the device through reliance on direct wafer stepper technology. As a result, the non-self aligned implanted channel does not require a high temperature drive, such that fabrication of the transistor is compatible with VLSI and ULSI processes, and the transistor can be up-integrated onto logic integrated circuits. Accuracy of the placement of the non-self aligned implanted channel provides for a shorter channel length, which enables the device to be highly area efficient while also increasing the current capability of the device. Furthermore, the transistor is characterized by a large field-induced avalanche breakdown voltage, enhanced by a thick gate oxide, a lightly doped drain, a field oxide region between the gate and the drain, and known field plating techniques.

Method of making a high voltage implanted channel device for VLSI and

The present invention relates to an integrated circuit which includes complementary MOS transistors (e.g., a CMOS circuit), an EEPROM, and to a method of making the integrated circuit. The EEPROM is incorporated in the circuit in such a manner that it does not adversely affect the high performance, low voltage operation of the CMOS circuit. Also, the EEPROM is designed so that it is programmable at a low voltage which is compatible with the low voltages typically used with the CMOS circuit. The EEPROM includes a floating gate and a control gate which have a large area of overlap so as to provide a high capacitance therebetween. This provides a high ratio (e.g., about two or greater) of the floating gate to control gate capacitance divided by the floating gate to substrate capacitance to provide the EEPROM with the low voltage operation. To make the integrated circuit, standard CMOS process steps using design rules of about two microns or less are used to make the MOS transistors. Additional steps are inserted in the standard CMOS process to form the EEPROM. The additional steps are inserted in such a manner so as not to adversely affect the operating characteristics of the resulting MOS transistors. For this purpose, any additional steps for forming the EEPROM which are carried out at a temperature of greater than 900.degree. C. are done so before the gate silicon dioxide layer of the MOS transistors is formed, and any further steps for forming the EEPROM are carried out at temperatures no greater than 900.degree. C.

Method of manufacturing CMOS integrated circuit with EEPROM

The present invention relates to an integrated circuit which includes complementary MOS transistors (e.g., a CMOS circuit), an EEPROM, and to a method of making the integrated circuit. The EEPROM is incorporated in the circuit in such a manner that it does not adversely affect the high performance, low voltage operation of the CMOS circuit. Also, the EEPROM is designed so that it is programmable at a low voltage which is compatible with the low voltages typically used with the CMOS circuit. The EEPROM includes a floating gate and a control gate which have a large area of overlap so as to provide a high capacitance therebetween. This provides a high ratio (e.g., about two or greater) of the floating gate to control gate capacitance divided by the floating gate to substrate capacitance to provide the EEPROM with the low voltage operation. To make the integrated circuit, standard CMOS process steps using design rules of about two microns or less are used to make the MOS transistors. Additional steps are inserted in the standard CMOS process to form the EEPROM. The additional steps are inserted in such a manner so as not to adversely affect the operating characteristics of the resulting MOS transistors. For this purpose, any additional steps for forming the EEPROM which are carried out at a temperature of greater than 900.degree. C. are done so before the gate silicon dioxide layer of the MOS transistors is formed, and any further steps of forming the EEPROM are carried out at temperatures no greater than 900.degree. C.

CMOS integrated circuit with EEPROM and method of manufacture

An integrated circuit is made that includes an insulated gate transistor and a buried contact. The buried contact is used to divide an active device area in two discrete parts, that are doped during source-drain doping in other active device mesas of the integrated circuit. Discrete contacts to these regions, along with the buried contact, provide an additional type of electrical component in the integrated circuit, such as a bipolar lateral transistor.

Uses for buried contacts in integrated circuits

An enhancement implant used in late programming of a ROM in an integrated circuit is combined with a depletion implant used much earlier in the fabrication process to also permit late programming of power paths in the integrated circuit. The implants must be matched and the IC heated after the enhancement implant.

Programming power paths in an IC by combined depletion and enhancement

A method of making a strain gauge in a fragile web wherein the improvement resides in making the web after the gauge is substantially completely formed. This reverse sequence is made possible by a unique combination of plasma deposited silicon oxide and plasma deposited silicon nitride on top of the completed device to protect it from attack during silicon substrate etching to form the diaphragm.

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Kokomo, IN, United States of America

Randy A Rusch