Chartered Semiconductor Manufacturing Ltd (corporation)

Chestnut Springs LLC

Other

Globalfoundries Singapore Pte. Ltd.

Randall Cher Liang Cha

Alex See

Yeow Kheng Lim

Tae Jong Lee

Lap Chan

Wang Ling Goh

Jia Zhen Zheng

Sufan Siauw

Ralph T Webdale

Elgin Kiok Quek

Yung Fu Chong

Mei-Sheng Zhou

Kin Leong Pey

Kheng Chok Tee

Chew Hoe Ang

Daniel Yen

Victor Seng Keong Lim

Chee Tee Chua

Eng-Hua Lim

Mei Sheng Zhou

Elgin Kiok Boone Quek

Shao-fu Sanford Chu

Eng Hua Lim

Chew-Hoe Ang

Jia-Zhen Zheng

Alex Kai Hung See

Cheng Yeow Ng

Chua Chee Tee

Cheng Cheh Tan

Daniel Lee-Wei Yen

A method for imparting flame retardancy to a substrate material. The method comprises adding to a substrate material a flame retardant composition. The flame retardant composition comprises at least one flame retardant salt, a nitrogen-containing compound, and optionally water. The at least one flame retardant salt comprises an ammonium salt of phosphoric acid. The ammonium salt of phosphoric acid comprises water soluble ammonium polyphosphate (APP). The water soluble ammonium polyphosphate has a total nitrogen as N from about 5 to about 15 weight percent, and a total phosphorus as POfrom about 30 to about 40 weight percent, based on the total weight of the ammonium polyphosphate (APP).

Method for imparting flame retardancy to a substrate material

A process for preparing a flame retardant composition, the process comprising: adding to a container at least one flame retardant salt, a nitrogen-containing compound, and optionally water; and mixing the contents of the container to give a dispersed mixture or dissolved solution comprising the flame retardant composition; wherein the at least one flame retardant salt comprises an ammonium salt of phosphoric acid; wherein the ammonium salt of phosphoric acid comprises water soluble ammonium polyphosphate (APP); wherein the water soluble ammonium polyphosphate has a total nitrogen as N from about 5 to about 15 weight percent, and a total phosphorus as POfrom about 30 to about 40 weight percent, based on the total weight of the ammonium polyphosphate (APP).

Process for preparing flame retardant compositions

This disclosure provides a composition comprising one or more substrate materials (e.g., polymers, rubbers, paper pulps, textiles, or polymer foams) and a flame retardant composition. The flame retardant composition includes at least one flame retardant salt (e.g., an ammonium salt of phosphoric acid such as water soluble ammonium polyphosphate), a nitrogen-containing compound (e.g., urea), and optionally water. This disclosure also provides a process for preparing the flame retardant composition, a process for imparting flame retardancy to a substrate material, and an intumescent process for forming an insulating protective layer on a substrate. This disclosure further provides fire retardant articles and processes for preparing fire retardant articles.

Flame retardant compositions and processes for preparation thereof

An integrated circuit is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.

Integrated circuit with self-aligned line and via

An integrated circuit and manufacturing method therefor is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.

Integrated circuit with self-aligned line and via and manufacturing method therefor

A gate structure having associated (LDD) regions and source and drain is formed as is conventional. A first oxide spacer, for example, is formed along the sidewalls of the gate structure. A layer of metal such as titanium is then deposited over the surface of the gate structure. Second sidewall spacers are formed covering the metal over the first sidewall spacer and covering the metal over isolation regions. A layer of polysilicon is deposited over the surface of the gate structure. A rapid thermal annealing (RTA) is performed causing the metal to react with both the silicon in the junction below the metal and the polysilicon above the metal forming a metal silicide. Metal along the sidewalls between the first and second sidewall spacers and over the isolation regions does not react and is etched away. By providing an additional source of silicon in the polysilicon layer above the metal, a thicker silicide is achieved.

Technique to achieve thick silicide film for ultra-shallow junctions

A silicon-on-insulator semiconductor device is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.

Dual silicon-on-insulator device wafer die

A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.

Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing

A method for forming a transistor having an elevated source/drain structure is described. A gate electrode is formed overlying a substrate and isolated from the substrate by a gate dielectric layer. Isolation regions are formed in and on the substrate wherein the isolation regions have a stepped profile wherein an upper portion of the isolation regions partly overlaps and is offset from a lower portion of the isolation regions in the direction away from the gate electrode. Ions are implanted into the substrate between the gate electrode and the isolation regions to form source/drain extensions. Dielectric spacers are formed on sidewalls of the gate electrode and the isolation regions. A conductive layer is deposited overlying the substrate, the gate electrode, and the isolation regions and planarized to leave the conductive layer adjacent to the gate electrode and separated from the gate electrode by the dielectric spacers wherein the conductive layer forms elevated source/drain junctions and wherein the elevated source/drain junctions completely overlie the source/drain extensions and wherein an upper portion of the elevated source/drain junctions extends into the stepped portion of the isolation regions thereby completing formation of a MOSFET having an elevated source/drain structure.

Method to fabricate elevated source/drain transistor with large area for silicidation

A method for forming a MOSFET having an elevated source/drain structure is described. A sacrificial oxide layer is provided on a substrate. A polish stop layer is deposited overlying the sacrificial oxide layer. An oxide layer is deposited overlying the polish stop layer. An opening is formed through the oxide layer and the polish stop layer to the sacrificial oxide layer. First polysilicon spacers are formed on sidewalls of the opening wherein the first polysilicon spacers form an elevated source/drain structure. Second polysilicon spacers are formed on the first polysilicon spacers. The oxide layer and sacrificial oxide layer exposed within the opening are removed. An epitaxial silicon layer is grown within the opening. A gate dielectric layer is formed within the opening overlying the second polysilicon spacers and the epitaxial silicon layer. A gate material layer is deposited within the opening. The gate material layer, first polysilicon spacers and second polysilicon spacers are polished back to the polish stop layer thereby completing formation of a MOSFET having an elevated source/drain structure in the fabrication of an integrated circuit device.

Method to fabricate elevated source/drain structures in MOS transistors

A method for forming a single gate having a dual work-function is described. A gate electrode is formed overlying a gate dielectric layer on a substrate. Sidewalls of the gate electrode are selectively doped whereby the doped sidewalls have a first work-function and whereby a central portion of the gate electrode not doped has a second work-function to complete formation of a single gate having multiple work-functions in the fabrication of integrated circuits.

Method to fabricate a single gate with dual work-functions

A method to form SOI devices using wafer bonding. A first substrate is provided having trenches in a first side. A first insulating layer is formed over the first side of the first substrate and filling the trenches. We planarize the first insulating layer to form isolation regions (e.g., STI). The three embodiments of the invention planarize the first insulating layer to different levels. In the second embodiment, the first insulating layer is etched back to form a recess. This recess later forms an air gap. We provide a second substrate having a second insulating layer over a first side of the second substrate. We bond the second insulating layer to the first insulating layer. Next, we thin the first substrate from the second side to expose the first insulating layer to form active areas between the isolation regions. Lastly, devices are formed in and on the active areas.

Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance

A silicon-on-insulator semiconductor device and manufacturing method therefor is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.

A method of manufacturing conductive lines that are thicker (not wider) in the critical paths areas. We form a plurality of first level conductive lines over a first dielectric layer. The first conductive lines run in a first direction. The first level conductive lines are comprised of a first level first conductive line and a second first level conductive line. We form a second dielectric layer over the first level conductive lines and the first dielectric layer. Next, we form a via opening in the second dielectric layer over a portion of the first level first conductive line. A plug is formed filling the via opening. We form a trench pattern in the second dielectric layer. The trench pattern is comprised of trenches that are approximately orthogonal to the first level conductive lines. We fill the trenches with a conductive material to form supplemental second lines. We form second level conductive lines over the supplemental second lines and the plug. The second level conductive lines are aligned parallel to the supplemental second lines. The supplemental second lines are formed under the critical path areas of the second level conductive lines. The second level conductive lines are not formed to contact the first level conductive lines where a contact is not desired. In the critical path areas of the second level conductive lines, the supplemental second lines underlie the second level conductive lines thereby increasing the effective overall wiring thickness in the critical path area thereby improving performance.

Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application

A method to form a silicon on insulator (SOI) device using wafer bonding. A first substrate is provided having an insulating layer over a first side. A second substrate is provided having first isolation regions (e.g., STI) that fill first trenches in the second substrate. Next, we bond the first and second substrate together by bonding the insulating layer to the first isolation regions and the second substrate. Then, a stop layer is formed over the second side of the second substrate. The stop layer and the second side of the second substrate are patterned to form second trenches in the second substrate. The second trenches have sidewalls at least partially defined by the isolation regions and the second trenches expose the second insulating layer. The second trenches define first active regions over the first isolation regions (STI) and define second active regions over the insulating layer. Next, the second trenches are filled with an insulator material to from second isolation regions. Next, the stop layer is removed. Lastly, devices are formed in and on the active regions.

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Singapore, Singapore

Randall Cher Liang Cha