Sun Microsystems, Inc.

Oracle International Corporation

Oracle America, Inc.

Rambabu Pyapali

Peter F Lai

Aveek Sarkar

Xuejun Yuan

Xiaowei Jin

Raymond A Heald

Shyam Sundar

Yongning Sheng

James M Kaku

Aharon Ostrer

Thelma C Taylor

Helen Dunn

Yongjun Zhang

Shian-Jiun Fu

Jeffrey F Wong

Xiaochun Gao

Ju H Yew

Teong Ming Cheah

Xi-An Xu

Samer H Haddad

Devices, systems, methods, and other embodiments associated with spare gates are described. In one embodiment, a spare gate in an integrated circuit has a disconnected discharge path to minimize or eliminate current leakage.

Low leakage spare gates for integrated circuits

An automatic custom block composition tool for composing custom blocks of an integrated circuit (IC) design that may include non-standard library cells. The tool includes program instructions that are executable to create and use a placement control file that includes instructions for use by the custom block composition tool to place the one or more non-standard library cells into the custom block layout. In addition, the program instructions may instantiate a leafcell for each non-standard and each standard library cell included in a netlist. The program instructions may access the placement control file and place each leafcell in a row of the custom block layout according to the placement control file. The program instructions may also pre-route power, clock and critical network signals, and generate a router control file used during remaining routing of the custom block by a conventional router tool.

Automatic block composition tool for composing custom blocks having non-standard library cells in an integrated circuit design flow

The timing response of a circuit path is predicted by modeling the circuit path using two different timing models. The variation between the timing responses produced by each of the timing models is used to generate a correction factor, which is then applied to one of the timing models. Once the correction factor has been applied to a timing model, the model is used to produce a corrected timing prediction for the modeled circuit path.

Method and software for predicting the timing delay of a circuit path using two different timing models

The capacitances of one or more inputs/outputs of a circuit are estimated by using an extraction tool () to extract information associated with the inputs/outputs from a netlist. The information includes information associated with circuit devices directly connected to the inputs/outputs, particularly information related to device connectivity and the feature sizes of the device. Once the information is extracted, a capacitance determination element () aggregates the feature sizes of all the circuit devices connected to each respective input or output, to obtain aggregate feature sizes for each respective input/output. The aggregate feature size is used in determining the total capacitance of the input/output. The total capacitance thus determined can be provided to a timing analysis tool (), which uses the total capacitance of each input or output to generate a timing model for the circuit.

Estimating capacitances using information including feature sizes extracted from a netlist

The present invention describes a method and an apparatus for determining switching power consumption of global devices (e.g., repeaters, flops or the like) in an integrated circuit design during high-level design phase after the global routing for the integrated circuit is available. The clock cycle is divided into various timing intervals and the timing reports are generated for each cycle to determine a time-domain staggered distribution of each device's switching activity within a given timing interval. Each device's switching activity is analyzed within the given timing interval (or segment thereof). The power consumption is determined for each device that switches in the given timing interval.

Method and apparatus for power consumption analysis in global nets

The present application describes various embodiments of a method and an apparatus for determining electromigration risks for signal nets in integrated circuits. A model for each one of the global nets connecting various circuit blocks in an integrated circuit is created using circuit blocks' timing model and detailed standard parasitic format representation (DSPF) of each global net. The final layout of the integrated circuit is not necessary to determine the electromigration risks. The models can be generated during the early stages of the design cycle once the DSPF of the global nets is available.

Method and apparatus for signal electromigration analysis

The present invention relates to a method and apparatus for a reconfigurable multi-chip module. The reconfigurable multi-chip module includes a processor; a memory module connected to the processor; and a memory control component for controlling whether the processor uses the memory module. The method of producing multi-chip modules includes assembling a processor and a memory module on the multi-chip module; testing the memory module; and selectively configuring the processor to use the memory module based on the testing of the memory module.

Reconfigurable multi-chip modules

Method for double-layer implementation of metal options in an integrated chip for efficient silicon debug

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Cupertino, CA, United States of America

Rambabu Pyapali