International Business Machines Corporation

Other

Infineon Technologies Ag

Elpis Technologies Inc.

Globalfoundries Inc.

Stmicroelectronics Gmbh

Infineon Technologies North America Corp.

Rama Divakaruni

Jack Allan Mandelman

Carl John Radens

Rajarao Jammy

Jochen C Beintner

Kangguo Cheng

William R Tonti

Larry Alan Nesbit

Jed Hickory Rankin

Arne Watson Ballantine

James William Adkisson

Marwan H Khater

Byeong Yeol Kim

Hiroyuki Akatsu

Paul David Agnello

Erin C Jones

Rajeev Malik

Johnathan E Faltermeier

Rajesh Rengarajan

Edward J Nowak

Oleg Gluschenkov

Gregory Gower Freeman

Yujun Li

Akira Sudo

Lawrence Alfred Clevenger

Rajiv V Joshi

Sampath Purushothaman

Michael Patrick Chudzik

Subramanian Srikanteswara Iyer

Herbert Lei Ho

Louis Lu-Chen Hsu

Babar Ali Khan

Robert H Dennard

Thomas W Dyer

Helmut Horst Tews

Chandrasekhar Narayan

Anna Wanda Topol

Louis C Hsu

Bruce Kenneth Furman

Michael P Belyansky

Ulrike Gruening

Stephan Kudelka

Joseph Francis Shepard, Jr

David R Greenberg

Mary Elizabeth Weybright

Philip L Flaitz

Mihel Seitz

Uwe Schroeder

Christopher M Schnabel

Michael Maldei

Giuseppe La Rosa

Carol J Heenan

Yoichi Takegawa

Bruce Bennett Doris

Jeffrey P Gambino

Nicolas J Loubet

Dureseti Chidambarrao

Ajey Poovannummoottil Jacob

Laertis Economikos

Gary Bela Bronner

Dae-Gyu Park

David M Dobuzinsky

Prasanna Khare

Scott David Halle

Jay William Strane

Wolfgang Bergner

Tzyy-Ming Cheng

Venkatachalam C Jaiprakash

Chienfan Yu

Jeremy K Stephens

Munir D Naeem

Dale Warner Martin

Andreas Knorr

Irene Lennox McStay

Radhika Srinivasan

Larry Clevenger

Sundar Kumar Iyer

Padraic C Shafer

Kil-Ho Lee

Giuseppe LaRosa

Dirk Tobben

Venkatachajam C Jaiprakash

Kenneth T Settlemeyer, Jr

Ryota Katsumata

Gerd Fehlauer

Ulrike Grüning

A semiconductor device includes a gate stack arranged on a channel region of a semiconductor layer and a semiconductor layer arranged on an insulator layer. A crystalline source/drain region is arranged in a cavity in the insulator layer, and a spacer is arranged adjacent to the gate stack, the spacer arranged over the source/drain region. A second insulator layer is arranged on the spacer and the gate stack, and a conductive contact is arranged in the source/drain region.

Conductive contacts in semiconductor on insulator substrate

Methods and semiconductor structures formed from the methods are provided which facilitate fabricating semiconductor fin structures. The methods include, for example: providing a wafer with at least one semiconductor fin extending above a substrate; transforming a portion of the semiconductor fin(s) into an isolation layer, the isolation layer separating a semiconductor layer of the semiconductor fin(s) from the substrate; and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the semiconductor fin(s), and a fin device(s) of a second architectural type in a second fin region of the semiconductor fin(s), where the first architectural type and the second architectural type are different fin device architectures.

Fin isolation structures facilitating different fin isolation schemes

A method is provided for making a bipolar transistor which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The collector pedestal can be formed on a surface of a collector active region exposed within an opening extending through first and second overlying dielectric regions, where the opening defines vertically aligned edges of the first and second dielectric regions.

Method of fabricating self-aligned bipolar transistor having tapered collector

A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETs. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin silicon on insulator (SOI) chip. Isolation trenches at each end of the FETs, i.e., at the end of the RSD regions, isolate and define FET islands. Insulating sidewalls at each RSD region sandwich the FET gate between the RSD regions. The gate dielectric may be a high K dielectric. Salicide on the RSD regions and, optionally, on the gates reduce device resistances.

High performance FET with elevated source/drain region

A method is provided for fabricating a bipolar transistor that includes growing an epitaxial layer onto an underlaying region having a low dopant concentration and a trench isolation region defining the edges of an active region layer, implanting a portion of the epitaxial layer through a mask to define a collector region having a relatively high dopant concentration, the collector region laterally adjoining a second region of the epitaxial layer having the low dopant concentration; forming an intrinsic base layer overlying the collector region and the second region, the intrinsic base layer including an epitaxial region in conductive communication with the collector region; forming a low-capacitance region laterally separated from the collector region by the second region, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer; and forming an emitter layer overlying the intrinsic base layer.

Method of fabricating a bipolar transistor having reduced collector-base capacitance

A bipolar transistor is provided which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The bipolar transistor further includes an intrinsic base overlying the upper surface of the collector pedestal, a raised extrinsic base conductively connected to the intrinsic base and an emitter overlying the intrinsic base. In a particular embodiment, the emitter is self-aligned to the collector pedestal, having a centerline which is aligned to the centerline of the collector pedestal.

Structure and method of self-aligned bipolar transistor having tapered collector

A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

Method of fabricating semiconductor side wall fin

Structure and method are provided for forming a bipolar transistor. As disclosed, an intrinsic base layer is provided overlying a collector layer. A low-capacitance region is disposed laterally adjacent the collector layer. The low-capacitance region includes at least one of a dielectric region and a void disposed in an undercut underlying the intrinsic base layer. An emitter layer overlies the intrinsic base layer, and a raised extrinsic base layer overlies the intrinsic base layer.

Bipolar transistor having reduced collector-base capacitance

A trench capacitor vertical-transistor DRAM cell in a SiGe wafer compensates for overhang of the pad nitride by forming an epitaxial strained silicon layer on the trench walls that improves transistor mobility, removes voids from the poly trench fill and reduces resistance on the bitline contact.

Structure of vertical strained silicon devices

A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.

Double gate trench transistor

A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.

High density chip carrier with integrated passive devices

Growing community of inventors

Ossining, NY, United States of America

Rama Divakaruni