Intel Corporation

Ralph Lane

Charles Christopher Hill

Tony Dambrauskas

The present invention uses a two step plasma etch process to create a via contact with an integral bump. After the via and bump have been plated, the semiconductor substrate is planarized to remove the excess metal, using the semiconductor substrate as a planar stop. The bulk silicon substrate surrounding the bumps are plasma etched back to expose the bumps for assembly.

Multi-step etch for metal bump formation

Embodiments of a method of forming a tapered via using a receding mask are disclosed. In one embodiment, an etch mask formed on a substrate includes a first aperture in a first photoresist layer and a second, larger aperture in an overlying second photoresist layer. Peripheries of the first and second apertures may be tapered as a result of an out-of-focus exposure. An etching process may be performed to create a tapered via in the substrate, and during this etching process, the first, relatively thinner photoresist layer will recede outwardly toward the aperture in the second photoresist layer. Other embodiments are described and claimed.

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Gilbert, AZ, United States of America

Ralph Lane