Infineon Technologies Ag

Infineon Technologies Austria Ag

Qimonda Ag

Infineon Technoloiges Austria Ag

Tinfineon Technologies Austria Ag

Ralf Otremba

Klaus Schiess

Josef Hoeglauer

Xaver Schloegel

Juergen Schredl

Teck Sim Lee

Joachim Mahler

Edward Fuergut

Khalil Hosseini

Uwe Kirchner

Chooi Mei Chong

Josef Höglauer

Oliver Haeberlen

Markus Dinkel

Alexander Heinrich

Helmut Strack

Martin Gruber

Bernd Schmoelzer

Fabio Brucchi

Michael Treu

Matteo-Alessandro Kutschak

Edmund Riedl

Lee Shuang Wang

Fabian Schnoy

Manfred Mengel

Thorsten Scharf

Erwin Huber

Wu Hu Li

Werner Josef Reiss

Franz Stueckler

Andreas Schloegl

Khai Huat Jeffrey Low

Hans-Joachim Schulze

Anton Mauder

Petteri Palm

Matthias Stecher

Thomas Basler

Irmgard Escher-Poeppel

Gerhard Noebauer

Henrik Ewe

Johannes Lodermeyer

Sanjay Kumar Murugan

Daniel Pedone

Thorsten Meyer

Horst Theuss

Eung San Cho

Rainald Sander

Uwe Wahl

Oliver Häberlen

Christian Fachmann

Dominic Maier

Erich Griebl

Adolf Koller

Stefan Landau

Reimund Engl

Reinhard Ploss

Chii Shang Hong

Manfred Kotek

Chee Voon Tan

Josef Maerz

Tomasz Naeve

Thai Kee Gan

Elvir Kahrimanovic

Paul Frank

Roland Rupp

Martin Standing

Georg Meyer-Berg

Gerhard Prechtl

Markus Brunnbauer

Jens Peter Konrath

Guenther Ruhl

Michael Lenz

Hans-Joerg Timme

Alexander Komposch

Daniel Domes

Thomas Bemmerl

Thomas Kilger

Andreas Riegler

Paul Ganitzer

Chee Yang Ng

Matthias Strassburg

Stefan Paulus

Peter Friedrichs

Stefan Woehlert

Wolfram Hable

Bernd Stadler

Ralf Wombacher

Ulrich Wachter

Wolfgang Scholz

Werner Kroeninger

Stanley Job Doraisamy

Michael Juerss

Ottmar Geitner

Ke Yan Tean

Manfred Schindler

Frank Kahlmann

Jayaganasan Narayanasamy

Davide Chiola

Gerhard Nöbauer

Lutz Goergens

A power device package includes first and second power transistor chips each having a control electrode, a first load electrode and a second load electrode. A control package terminal is electrically coupled to the control electrode of the first power transistor chip via a first wire bond connection and to the control electrode of the second power transistor chip via a second wire bond connection. A first package terminal is electrically coupled to the first load electrode of the first and second power transistor chips. A second package terminal is electrically coupled to the second load electrode of the first power transistor chip and/or the second power transistor chip. A length of the first wire bond connection is greater than a length of the second wire bond connection, and a cross-sectional area of the first wire bond connection is greater than a cross-sectional area of the second wire bond connection.

Multi-chip device with gate redistribution structure

A semiconductor package includes: a leadframe having first, second and third die pads and leads, each die pad having upper and lower surfaces; first and second power semiconductor devices; a control semiconductor device; and a mold compound. The upper surface of each die pad is arranged within the mold compound. The lower surface of the second die pad is spaced apart from a side face of the semiconductor package by a distance that is greater than a length of the individual leads. The first power semiconductor device is mounted on the upper surface of the first die pad and electrically coupled to the second die pad by one or more first connectors extending between the first device and the upper surface of the second die pad. The upper surface of the second die pad is occupied by the one or more connectors or in direct contact with the mold compound.

Semiconductor package and method of manufacturing a semiconductor package

A package is disclosed. In one example, the package comprises a first load terminal, a second load terminal, a power component mounted on the first load terminal, and a logic component electrically conductively mounted on one of the first load terminal. The logic component is the second load terminal and electrically connected with the power component for controlling the power component.

Package with load terminals on which coupled power component and logic component are mounted

A cryostat socket for holding an ion trap device mounted on a substrate in a cryostat includes a housing frame provided for pre-assembly in the cryostat. A pin insert is arranged in the housing frame. The pin insert includes a base plate and contact pins. The contact pins are arranged in an array. A housing cover has a receptacle for the substrate. The housing cover, when assembled with the housing frame, exerts a compressive force on a front side of the substrate by which a rear side of the substrate is pressed onto the contact pins.

Cryostat socket for holding an ion trap device mounted on a substrate in a cryostat

A semiconductor package is provided. The semiconductor package may include at least one semiconductor chip including a contact pad configured to conduct a current, a conductor element, wherein the conductor element is arranged laterally overlapping the contact pad and with a distance to the contact pad, at least one electrically conductive spacer, a first adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the contact pad, and a second adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the conductor element, wherein the conductor element is electrically conductively connected to a clip or is at least part of a clip, and wherein the spacer is configured to electrically conductively connect the contact pad with the laterally overlapping portion of the conductor element.

Semiconductor package

A semiconductor package includes a power semi conductor chip comprising SiC, a leadframe part including Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint includes at least one intermetallic phase.

Semiconductor package and method for fabricating a semiconductor package

A semiconductor chip includes a semiconductor body having a main surface and a rear surface opposite the main surface, a first bond pad disposed on the main surface, a second bond pad disposed on the rear surface, a first switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the first bond pad, and a second switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the second bond pad.

Multi-device semiconductor chip with electrical access to devices at either side

A chip package including a semiconductor chip is provided. The chip package may include a packaging material at least partially around the semiconductor chip with an opening extending from a top surface of the packaging material to the semiconductor chip and/or to an electrical contact structure contacting the semiconductor chip, and a thermally conductive material in the opening, wherein the thermally conductive material is configured to transfer heat from the semiconductor chip to an outside, wherein the thermally conductive material extends laterally at least partially over the top surface of the packaging material.

Chip package and semiconductor arrangement having thermally conductive material in contact with a semiconductor chip and methods of forming thereof

A semiconductor device assembly includes a cooling system, a plurality of semiconductor packages, each including a semiconductor die and an encapsulant body, and a multi-device thermal interface interposed between the plurality of semiconductor packages and the cooling system, wherein the semiconductor packages are each configured as surface mount devices, and wherein the multi-device thermal interface thermally couples each of the semiconductor packages to the cooling system.

Semiconductor assembly with multi-device cooling

A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.

Semiconductor package having a chip carrier with a pad offset feature

A semiconductor device package includes a printed circuit board including a first central area, a second lateral area, and a third lateral area, a semiconductor die including a first main face and a second main face opposite the first main face, a first contact pad on the first main face and a second contact pad on the second main face, the semiconductor die disposed in the first central area of the printed circuit board, a first metallic side wall of the semiconductor device package disposed in the second lateral area of the printed circuit board, a second metallic side wall of the semiconductor device package disposed in the third lateral area of the printed circuit board, wherein at least one of the first metallic side wall and the second metallic side wall is electrically connected with one of the first contact pad or the second contact pad.

Semiconductor device package comprising side walls connected with contact pads of a semiconductor die

A package for mounting on a mounting base is disclosed. In one example, the package comprises a carrier, an electronic component mounted at the carrier, leads electrically coupled with the electronic component and to be electrically coupled with the mounting base, and a linear spacer for defining a spacing with respect to the carrier.

Linear spacer for spacing a carrier of a package

A molded semiconductor package includes: a semiconductor die embedded in a mold compound; a first heat spreader partly embedded in the mold compound and thermally coupled to a first side of the semiconductor die; and a second heat spreader partly embedded in the mold compound and thermally coupled to a second side of the semiconductor die opposite the first side. The first heat spreader includes at least one heat dissipative structure protruding from a side of the first heat spreader uncovered by the mold compound and facing away from the semiconductor die. The mold compound is configured to channel a fluid over the at least one heat dissipative structure in a direction parallel to the first side of the power semiconductor die. Corresponding methods of production and electronic assemblies are also described.

Molded semiconductor package with dual integrated heat spreaders

A semiconductor includes a carrier; a semiconductor element arranged on the carrier; a first row of terminals arranged along a first side face of the carrier; a second row of terminals arranged along a second side face of the carrier opposite the first side face; and an encapsulation body encapsulating the semiconductor element, wherein the semiconductor element comprises a first transistor structure and a second transistor structure, wherein the first row of terminals comprises a first gate terminal, a first sensing terminal coupled, and a first power terminal, wherein the second row of terminals, a second sensing terminal, and a second power terminal.

Semiconductor device including a bidirectional switch

A semiconductor device includes: a carrier including an electronic circuit; a plurality of semiconductor chip packages mounted on the carrier, each of the chip packages including an encapsulation encapsulating the semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip with the electronic circuit, and at least one cooling structure protruding from the encapsulation; and a cooling element thermally conductively connected to at least one cooling structure of each of at least two of the plurality of semiconductor chip packages.

Semiconductor device having a carrier, semiconductor chip packages mounted on the carrier and a cooling element

Growing community of inventors

Kaufbeuren, Germany

Ralf Otremba