Infineon Technologies Ag

Ralf Henninger

Franz Hirler

Walter Rieger

Joachim Krumrey

Markus Zundel

Martin Pölzl

Jenoe Tihanyi

Martin Poelzl

Frank Dieter Pfirsch

Gerald Deboy

Armin Willmeroth

Uwe Wahl

Markus Schmitt

Uli Hiller

Carolin Tolksdorf

Manfred Kotek

Heimo Hofer

Jan Ropohl

Joost Larik

Martin P&ouml;lzl

A semiconductor component is described. In one embodiment, the semiconductor component includes a semiconductor body with a first side and a second side. A drift zone is provided, which is arranged in the semiconductor body below the first side and extends in a first lateral direction of the semiconductor body between a first and a second doped terminal zone. At least one field electrode is provided, which is arranged in the drift zone, extends into the drift zone proceeding from the first side and is configured in a manner electrically insulated from the semiconductor body.

Lateral semiconductor component with a drift zone having at least one field electrode

A trench transistor has a cell array, in which at least one cell array trench () is provided, and an edge structure framing the cell array. An edge trench () spaced apart from the cell array trenches () is provided in the edge structure.

Trench transistor

The invention relates to a method for fabricating a drift zone of a vertical semiconductor component and to a vertical semiconductor component having the following features:

Vertical semiconductor component having a drift zone having a field electrode, and method for fabricating such a drift zone

The power transistor has a trench cell in a semiconductor body. A lower edge of the gate electrode has a profile which is not horizontal, i.e., not planar with respect to the field electrode.

Power transistor

A method for fabricating gate electrodes () in a field plate trench transistor () having a cell array with a plurality of trenches () and a plurality of mesa regions () arranged between the trenches comprises the following steps: application of a gate electrode layer () to the cell array in such a way that the gate electrode layer () has depressions within or above the trenches (), application of a mask layer () to the cell array, etching-back of the mask layer () in such a way that mask layer residues () remain only within the depressions of the gate electrode layer (), and etching-back of the gate electrode layer () using the mask layer residues () as an etching mask in such a way that gate electrode layer residues () remain only within/above the trenches ().

Method for fabricating gate electrodes in a field plate trench transistor, and field plate trench transistor

A method for fabricating a transistor configuration including at least one trench transistor cell has a gate electrode and a field electrode disposed in a trench below the gate electrode. The trenches are formed in a semiconductor substrate. A drift zone, a channel zone, and a source zone are in each case provided in the semiconductor substrate. According to the invention, the source zone and/or the channel zone are formed at the earliest after the introduction of the trenches into the semiconductor substrate by implantation and diffusion.

Method for fabricating a transistor configuration including trench transistor cells having a field electrode, trench transistor, and trench configuration

A method for fabricating a field-effect-controllable semiconductor component includes providing a configuration having a semiconductor body with a front side, a rear side, a first terminal zone of a first conduction type, a channel zone of a second conduction type formed above the first terminal zone, and at least one control electrode adjacent the channel zone. The control electrode is insulated from the semiconductor body. A second terminal zone of the first conduction type is fabricated in the channel zone near the front side of the semiconductor body by: doping the channel zone near the front side with a first dopant concentration to fabricate a first zone of the first conduction type, and doping a section of the first zone with a second dopant concentration higher than the first dopant concentration to form a second zone of the first conduction type.

Field-effect-controllable semiconductor component and method for fabricating the component

A trench transistor has a source zone introduced from a doped spacer into a body region and a channel running vertically along the insulation layer of the trench. A method is taught for fabricating the trench transistor of this type.

Trench transistors and methods for fabricating trench transistors

Transistor configurations have trench transistor cells disposed along trenches in a semiconductor substrate with two or more electrode structures disposed in the trenches, and also metallizations are disposed above a substrate surface of the semiconductor substrate. The trenches extend into an inactive edge region of the transistor configuration and an electrically conductive connection between the electrode structures and corresponding metallizations are provided in the edge region.

Transistor configuration with a structure for making electrical contact with electrodes of a trench transistor cell

A trench power semiconductor component is described which has an edge cell in which an edge trench is provided. The edge trench, at least on an outer side wall, has a thicker insulating layer than an insulating layer of trenches of the cell array. This simple configuration provides a high dielectric strength and is economical to produce.

Trench power semiconductor

A semiconductor component has a cell array formed in a semiconductor body with a number of identical transistor cells and at least one edge cell formed at an edge of the cell array. Each of the transistor cells has a control electrode, which is formed in a trench, and the edge cell has a field plate, which is formed in a trench, with a distance between the trench of the edge cell and the trench of the immediately adjacent transistor cell being less than the distance between a trench of a transistor cell and the trench of an immediately adjacent transistor cell in the cell array.

Semiconductor component with an increased breakdown voltage in the edge area

The switching behavior of a transistor configuration is improved by providing a shielding electrode in an edge region. The shielding electrode surrounds at least sections of an active cell array. The capacitance between an edge gate structure and a drain zone and hence the gate-drain capacitance CGD of the transistor configuration is reduced by the shielding electrode located in the edge region.

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Munich, Germany

Ralf Henninger