Texas Instruments Corporation

Rajneesh Jaiswal

Eric W Beach

H Jerome Barber

Thomas E Kuehl

Barbara M Barnes

Chandrakant Patadia

According to various embodiments, the present teachings include methods for reducing first wafer defects in a high-density plasma chemical vapor deposition process. In an exemplary embodiment, the method can include running a deposition chamber for deposition of film on a first batch of silicon wafers and then cleaning interior surfaces of the deposition chamber. The method can further include inserting a protective electrostatic chuck cover (PEC) wafer on an electrostatic chuck in the deposition chamber and applying power to bias the PEC wafer while simultaneously precoating the deposition chamber with an oxide. The exemplary method can also include re-starting the deposition chamber for deposition of film on a second batch of silicon wafers.

Use of a biased precoat for reduced first wafer defects in high-density plasma process

A method of determining the degree of calibration of an RTP chamber () includes providing a test wafer having a deposited sichrome layer () of sheet resistance Rsi on an oxide layer () formed on a silicon substrate (). The test wafer is annealed in the RTP chamber for a selected duration at a selected anneal temperature which is measured by the a permanent thermocouple or pyrometer (). The sheet resistance of the annealed sichrome is measured, and a sheet resistance change &#x394;Rs=Rsi&#x2212;Rsf is computed. The 'actual' value of the anneal temperature is determined from predetermined characterizing information relating &#x394;Rs to a range of values of anneal temperature. The RTP chamber is re-calibrated if in accordance with the value of &#x394;Rs if the difference between the 'actual' value of the anneal temperature and the value measured by the permanent thermocouple or pyrometer exceeds an acceptable error. The basic technique can be utilized to determine an anneal time and anneal duration for annealing sichrome resistors to precisely adjust the sheet resistance or TCR thereof.

Rapid thermal anneal equipment and method using sichrome film

A method of preventing contact noise in a SiCr thin film resistor includes performing in situ depositions of a SiCr layer and then a TiW layer on a substrate without breaking a vacuum between the depositions, to prevent formation of any discontinuous oxide between the SiCr layer and the TiW layer. The SiCr and TiW layers are patterned to form a predetermined SiCr thin film resistor pattern and a TiW resistor contact pattern on the SiCr thin film resistor, and a metallization layer is provided to contact the TiW forming the resistor contact pattern.

Resistor integration structure and technique for noise elimination

Nickel silicide contact regions are formed on a source (), drain () and polycrystalline silicon gate () of an integrated circuit transistor by annealing it after a nickel layer has been deposited on the source, drain, and gate, with no cap layer on the nickel layer. Nickel silicide bridging between the gate and source and/or drain is avoided or eliminated by using a chrome etching process to remove un-reacted nickel and nickel remnants from exposed surfaces of dielectric spacers (A,B) located between the gate and source and between the gate and drain. The chrome etching process includes use of a solution including cerric ammonium nitrate, nitric acid, and acetic acid.

Nickel silicide method and structure

A thin film resistor and at least one metal interconnect are formed in an integrated circuit. A first dielectric layer is formed over a metal interconnect layer. A thin film resistor is formed on the first dielectric layer and a second dielectric layer formed over the thin film resistor. Thin film resistor vias and the at least one trench are formed concurrently in the second dielectric layer. A trench via is then formed in the at least one trench. The trench via, the at least one trench and the thin film resistor vias are filled with a contact material layer to form thin film resistor contacts and at least one conductive line coupled to the metal interconnect layer.

Thin film resistor integration in a dual damascene structure

A thin film resistor ( ) is formed over an etch stop layer . Contact pads ( ) are formed n the thin film resistor ( ) and a dielectric layer ( ) is formed over the thin film resistor ( ). Metal structures ( are formed above the thin film resistor ( ) and metal ( ) is used to fill a trench and via formed in the dielectric layer ( ).

Method for thin film resistor integration in dual damascene structure

A method for processing a partially fabricated semiconductor wafer having a layer of nichrome resistor material patterned to form a plurality of nichrome resistors on a surface of the wafer includes performing a wet pre-metallization cleaning step on the wafer surface, performing an RF argon plasma sputter etching process on the wafer surface, advancing the wafer into a second reactor without breaking a vacuum in either reactor, depositing a layer of metal on the surface, patterning the metal to form a predetermined metal interconnection pattern thereof, performing a stabilization bake cycles on the wafer, measuring the TCR of the nichrome resistor material, and rejecting the wafer if the measured TCR is greater than a predetermined value.

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Tucson, AZ, United States of America

Rajneesh Jaiswal