Intel Corporation

Rajiv Rastogi

Yang Cao

Jir-shyr Chen

Yue Ma

Valery M Dubin

Harry H Fujimoto

Paul McGregor

Sandra J Underwood

David Jentz

Ramesh Viswanathan

A method and apparatus are described that use cell voltage and/or current as monitor to prevent electrochemical deposition (e.g., electroplating) tools from deplating wafers with no or poor metal (e.g., Cu) seed coverage.

Using cell voltage as a monitor for deposition coverage

A copper electroplating bath composition and a method of copper electroplating to improve gapfill are provided. The method of electroplating includes providing an aqueous electroplating composition, comprising copper, at least one acid, at least one halogen ion, an additive including an accelerating agent, a suppressing agent, and a suppressing-accelerating agent, and the solution and mixture products thereof; contacting a substrate with the plating composition; and impressing a multi-step waveform potential upon the substrate, wherein the multi-step waveform potential includes an entry step, wherein the entry step includes a first sub-step applying a first current and a second sub-step applying second current, the second current being greater than the first current. The accelerating agent is provided in concentration of greater than 1.5 ml/liter, the suppressing agent is provided in concentration of greater than 15 ml/liter, and the accelerating-suppressing agent is provided in concentration of greater than 10 ml/liter.

Method of copper electroplating to improve gapfill

A method and apparatus are described that use cell voltage and/or current as monitor to prevent electrochemical deposition (e.g., electroplating) tools from deplating wafers with no or poor metal (e.g., Cu) seed coverage. In one embodiment, the voltage of a plating cell including a reference wafer which has substantially complete Cu seed coverage is measured. A reference resistance of the plating cell with the reference wafer is determined. The voltage of the plating cell including a calibration wafer which has no or insufficient seed coverage at its edge is measured. A calibration resistance of the plating cell with the calibration wafer is determined. An error trigger based on a comparison of the reference resistance with the calibration resistance is selected.

An improvement in a metal stack used for interconnecting structures in an integrated circuit. The improvement comprises the entrapping in a titanium layer of nitrogen at the interface where the titanium layer contacts a bulk conductor layer such as an aluminum-copper alloy layer. The entrapped nitrogen prevents the formation of any substantial amount of titanium aluminide thereby reducing current densities and also improving the electromigration properties of the stack. As currently preferred, the nitrogen is entrapped in approximately the first 30.ANG. of the titanium layer.

Interface between titanium and aluminum-alloy in metal stack for

The present invention generally involves the fabrication of semiconductor devices so as to reduce the active region to interconnect interface resistivity. Fabrication begins by forming active regions on a semiconductor device. Next, a titanium metal of approximately 900 .ANG. thickness is deposited on the semiconductor device. The semiconductor device is then annealed in a single step to form the interconnects.

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Portland, OR, United States of America

Rajiv Rastogi