International Business Machines Corporation

Infineon Technologies Ag

Other

Siemens Aktiengesellschaft

Rajiv M Ranade

Gangadhara Swami Mathad

Kevin K Chan

Munir D Naeem

Subhash Balakrishna Kulkarni

Mahmoud M Khojasteh

Nicholas C M Fuller

Siddhartha Panda

George Gabriel Totir

Gary Walter Behm

Pratik P Joshi

Teresita Quitua Magtoto

Venkatachalam C JaiPrakash

Ravikumar Ramachandran

Byeong Yeol Kim

K Paul Muller

Heon Lee

Xian Jay Ning

Stefan Schmitz

Alexander Michaelis

Sadanand Vinayak Deshpande

Gill Yong Lee

Satish D Athavale

Young-Jin Park

Brian S Lee

Kia-Seng Low

Joachim Nuetzel

Ihar Kasko

George Stojakovic

Bertrand Flietner

Keith Raymond Milkove

Russell D Allen

George Worth

Elizabeth Morales

Joachim Neutzel

Stephan P Kudelka

Kim Poong Mee Lee, Legal Representative

An organic planarizing layer (OPL) is formed atop a semiconductor substrate which includes a plurality of gate lines thereon. Each gate line includes at least a high k gate dielectric and a metal gate. A patterned photoresist having at least one pattern formed therein is then positioned atop the OPL. The at least one pattern in the photoresist is perpendicular to each of the gate lines. The pattern is then transferred by etching into the OPL and portions of each of the underlying gate lines to provide a plurality of gate stacks each including at least a high k gate dielectric portion and a metal gate portion. The patterned photoresist and the remaining OPL layer are then removed utilizing a sequence of steps including first contacting with a first acid, second contacting with an aqueous cerium-containing solution, and third contacting with a second acid.

Use of an organic planarizing mask for cutting a plurality of gate lines

A method and system for controlling a dimension of an etched feature. The method includes: measuring a mask feature formed on a top surface of a layer on a substrate to obtain a mask feature dimension value; and calculating a mask trim plasma etch time based on the mask feature dimension value, a mask feature dimension target value, a total of selected radio frequency power-on times of a plasma etch tool since an event occurring to a chamber or chambers of a plasma etch tool for plasma etching the layer, and an etch bias target for a layer feature to be formed from the layer where the layer is not protected by the mask feature during a plasma etch of the layer.

Method and system for line-dimension control of an etch process

A method of forming at least one deep trench structure having an increased trench depth is provided. The method includes providing at least one deep trench having sidewalls that extend to a common bottom wall in a surface of a substrate. Each deep trench has initial dimensions that are wider than targeted dimensions for the deep trenches. To reduce the initial dimensions to that of the targeted dimensions, an epitaxial silicon film is formed selectively or non-selectively on at least some portions of the sidewalls using a low-temperature ultra-high vacuum epitaxial silicon growth tehnique.

Method to achieve increased trench depth, independent of CD as defined by lithography

A method is provided for patterning a semiconductor region, which can be heavily doped. A patterned mask is provided above the semiconductor region. A portion of the semiconductor region exposed by the patterned mask is etched in an environment including a polymerizing fluorocarbon, e.g., a chlorine-free fluorocarbon having a high ratio of carbon to fluorine atoms, and at least one non-polymerizing substance selected from the group consisting of non-polymerizing fluorocarbons, e.g. those having a low ratio of carbon to fluorine atoms, and hydrogenated fluorocarbons. The method preferably passivates the sidewalls of the patterned semiconductor region, such that a lower region of semiconductor material below the patterned region can be directionally etched without eroding the thus passivated patterned region.

Method for patterning a semiconductor region

A method of fabricating a magnetic tunnel junction (MTJ) device is provided. A patterned hard mask is oxidized to form a surface oxide thereon. An MTJ stack is etched in alignment with the patterned hard mask after the oxidizing of the patterned hard mask. Preferably, the MTJ stack etch recipe includes chlorine and oxygen. Etch selectivity between the hard mask and the MTJ stack is improved.

Fabrication process for a magnetic tunnel junction device

A method of manufacturing a resistive semiconductor memory device (), comprising depositing an insulating layer () over a workpiece (), and defining a pattern for a plurality of alignment marks () and a plurality of conductive lines () within the insulating layer (). A conductive material is deposited over the wafer to fill the alignment mark () and conductive line () patterns. The insulating layer () top surface is chemically-mechanically polished to remove excess conductive material from the insulating layer () and form conductive lines (), while leaving conductive material remaining within the alignment marks (). A masking layer () is formed over the conductive lines (), and at least a portion of the conductive material is removed from within the alignment marks (). The alignment marks () are used for alignment of subsequently deposited layers of the resistive memory device ().

MRAM MTJ stack to conductive line alignment method

A method for etching trenches in a substrate secures a wafer to an electrode in a plasma chamber and heats the wafer to a temperature of greater than 200 degrees Celsius. The wafer is exposed to a reactive plasma to etch trenches into the substrate of the wafer with minimal redeposition of etch by-products to avoid pinching off the trench and to promote further etching.

Method for dry etching deep trenches in a substrate

The present invention provides methods of producing trench structures having substantially void-free filler material therein. The fillers may be grown from a liner material such as polysilicon formed along the sidewalls of the trench. Previously formed voids may be healed by exposing the voids and growing epitaxial silicon.

Method to fill deep trench structures with void-free polysilicon or silicon

Semiconductor devices having trenches with buried straps therein preventing lateral out-diffusion of dopant are provided along with methods of fabricating such semiconductor devices.

Circuit with buried strap including liner

A method of etching a deep, high aspect ratio opening in a silicon substrate includes etching the substrate with a first plasma formed using a first gaseous mixture including a bromine containing gas, an oxygen containing gas and a first fluorine containing gas. The etching process with the first gaseous mixture produces a sidewall passivating deposit, which builds up near the opening entrance. To reduce this buildup, and to increase the average etching rate, the sidewall passivating deposit is periodically thinned by forming a second plasma using a mixture containing silane and a second fluorine containing gas. The substrate remains in the same plasma reactor chamber during the entire process and the plasma is continuously maintained during the thinning step. Holes of a depth greater than 40 times the width may be produced using repeated cycles of etching and thinning.

Method of etching high aspect ratio openings

A method of fabricating a high aspect ratio deep trench in a semiconductor substrate comprising reducing the formation of a passivation film during the etching of the trench by including a first step of contacting the substrate in which the deep trench is to be formed with a fluorine poor or low concentration of a fluorine gas in the plasma of etchant gases for etching the high aspect ratio deep trench, followed by a second step of increasing the concentration of the fluorine containing gas to create a fluorine-rich plasma while lowering the chamber pressure of the reactor and RF power. Preferably, the second step is introduced periodically during the etching of a deep trench in an alternating manner.

Method to increase the etch rate and depth in high aspect ratio structure

Method of manufacturing circuit with buried strap including a liner

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Brewster, NY, United States of America

Rajiv M Ranade