International Business Machines Corporation

Other

Siemens Aktiengesellschaft

Infineon Technologies Ag

Kabushiki Kaisha Toshiba

Globalfoundries Inc.

Infineon Technologies North America Corp.

Siemens Microelectronics Limited

Rajesh Rengarajan

Alexander Reznicek

Min Yang

Chun-Yung Sung

Victor Chan

Meikei Ieong

Jack Allan Mandelman

Paul Michael Solomon

Rama Divakaruni

John Michael Hergenrother

Massimo V Fischetti

Omer H Dokumaci

Jeffrey P Gambino

Dureseti Chidambarrao

Brian Joseph Greene

Jochen C Beintner

Hiroyuki Akatsu

Venkatachalam C Jaiprakash

Yujun Li

Mary Elizabeth Weybright

Suryanarayan G Hegde

Paul Andrew Ronsheim

Hans-Oliver Joachim

Ramachandra Divakaruni

Xiangdong Chen

Gary Bela Bronner

Johnathan E Faltermeier

Ulrike Gruening

David M Dobuzinsky

Scott David Halle

Johann Alsmeier

Chienfan Yu

An L Steegen

Rajeev Malik

Dale Warner Martin

Joseph M Lukaitis

Kevin McStay

Radhika Srinivasan

Giuseppe La Rosa

Michael Maldei

Munir-ud-Din Naeem

Prakash Chimanlal Dev

Kil-Ho Lee

MeiKei Leong

Thomas Rupp

Giuseppe LaRosa

John Preston Benedict

Kilho Lee

Woo-Tang Kang

Ryota Katsumata

Hirofumi Inoue

The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.

Dual trench isolation for CMOS with hybrid orientations

The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a &#x3c;110&#x3e; crystal orientation and a biaxial compressive strain. The term 'biaxial compressive stress' is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing &#x3c;110&#x3e; layer; and creating a biaxial strain in the silicon-containing &#x3c;110&#x3e; layer.

Enhancement of electron and hole mobilities in &#x3c;110&#x3e; Si under biaxial compressive strain

Methods and structures for relieving stresses in stressed semiconductor liners. A stress liner that enhances performance of either an NFET or a PFET is deposited over a semiconductor to cover the NFET and PFET. A disposable layer is deposited to entirely cover the stress liner, NFET and PFET. This disposable layer is selectively recessed to expose only the single stress liner over a gate of the NFET or PFET that is not enhanced by such stress liner, and then this exposed liner is removed to expose a top of such gate. Remaining portions of the disposable layer are removed, thereby enhancing performance of either the NFET or PFET, while avoiding degradation of the NFET or PFET not enhanced by the stress liner. The single stress liner is a tensile stress liner for enhancing performance of the NFET, or it is a compressive stress liner for enhancing performance of the PFET.

Method and structure for reducing induced mechanical stresses

A method of manufacturing a device includes doping a low voltage threshold area and a high voltage threshold area. Gate structures are formed over the low voltage threshold and high voltage threshold areas while protecting the gate structure over the low voltage threshold area. A silicidation process is performed over the high voltage threshold area while the gate structure over the low voltage threshold area remains protected. Siliciding includes depositing metal on the gate of the high voltage threshold area and annealing the metal, the metal is deposited either by CVD or sputtering followed by anneal to fully suicide the gate structure of the high voltage threshold area. The metal, preferably cobalt or nickel is deposited to a thickness of approximately 500 &#x212b;, annealed for about 3 minutes at about 400&#xb0; C.

Method of manufacturing a multi-workfunction gates for a CMOS circuit

An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An oxide spacer is formed along sidewalls of the stacked structure. The nitride liner layer is patterned and etched to form at least one opening therein to the substrate while the nitride cap layer remains substantially intact.

Method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit line contact of DRAM device

A method for reducing hot carrier reliability problems within an integrated circuit device. The method includes forming a shallow trench isolation structure incorporated with the device by filling a trench with a photoresist plug and removing a portion of the photoresist plug to a level below the depth of a channel also incorporated with the device. A nitride liner disposed within the trench under the photoresist plug is then recessed to a level substantially equal to the level of the photoresist material, which is then removed. The method further includes the deposition of oxide fill within the trench, thereby encapsulating the recessed nitride liner.

Recessed shallow trench isolation structure nitride liner and method for making same

A method for manufacturing an integrated circuit having a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor on a semiconductor wafer by creating a spacer having a first width for the n-type field effect transistor and creating a spacer having a second width for the p-type field effect transistor, the first width being greater than the second width and depositing silicide material on the semiconductor wafer such that tensile mechanical stresses are formed within a channel of the n-type field effect transistor and compressive stresses are formed within a channel of the p-type field effect transistor.

Silicide proximity structures for CMOS device performance improvements

In a method of making a dual work function gate electrode of a CMOS semiconductor structure, the improvement comprising formation of the dual work function gate electrode so that there is no boron penetration in the channel region and no boron depletion near the gate oxide, comprising: a) forming a gate oxide layer over a channel of a nMOS site and over a channel of a pMOS site; b) forming an undoped polysilicon layer over the gate oxide layer; c) masking the pMOS site, forming an a-Si layer over the nMOS site using a first heavy ion implantation, and implanting arsenic solely into the a-Si layer; d) masking the nMOS site formed by step c), forming an a-Si layer over the pMOS site using a second heavy ion implantation, and implanting boron solely into the a-Si regions; e) laser annealing the nMOS and pMOS sites for a short time and at an energy level sufficient to melt at least a portion of the a-Si but insufficient to melt the polysilicon; and f) affecting cooling after laser annealing to convert a-Si into polysilicon without gate oxide damage.

Formation of dual work function gate electrode

Body effects in vertical MOSFET transistors are considerably reduced and other device parameters are unaffected in a vertical transistor having a threshold implant with a peak at the gate and an implant concentration distribution that declines rapidly away from the gate to a plateau having a low p-well concentration value. A preferred embodiment employs two body implants&mdash;an angled implant having a peak at the gate that sets the Vt and a laterally uniform low dose implant that sets the well dopant concentration.

Vertical MOSFET with horizontally graded channel doping

P-type metal-oxide semiconductor field effect transistor (PMOSFET) devices have a characteristic property known as threshold voltage. This threshold voltage may consist of separate threshold voltages associated with the main portion of the gate region of the device and with the sidewall corner of the device. Under some conditions, the threshold behavior in the sidewall corner region of the device may dominate the performance of the device, not necessarily in the manner intended by the designer of the device. A method of controlling threshold voltage behavior is described. In particular, ion implantation of nitrogen in the gate sidewall region of the device can provide such control. Devices made by this method are also described.

PMOSFET device with localized nitrogen sidewall implantation

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Poughkeepsie, NY, United States of America

Rajesh Rengarajan