National Semiconductor Corporation

Rajesh R Berigei

Marcel A Ter Beek

Elroy M Lucero

Jang Dae Kim

Steve A Martinez

Satya N Mishra

Sury Maturi

Alan P Bucholz

Hui X Li

An Algorithmic Reactive Testbench (ART) system is provided for the simulation/verification of an analog integrated circuit design. The ART system is a high level simulation/verification environment with a user program in which one or more analog testbenches are instantiated and operated as prescribed in an algorithmic reactive testbench program, and the properties of the unit testbenches (test objects) can be influenced by prior analysis of themselves or other tests. The test object may also contain various properties including information reflecting the status of the test object. The modification of a property of a test object is an act of communication in the ART system from the algorithmic reactive testbench program to the test object.

Algorithmic reactive testbench for analog designs

An automated method for checking electrostatic discharge (ESD) guidelines ensures that a sufficient number of ESD protection cells have been provided in the neighborhood of each pad in an integrated circuit design to ensure adequate current sinking and voltage clamping during the occurrence of an ESD event.

Dynamic computation of ESD guidelines

Growing community of inventors

San Jose, CA, United States of America

Rajesh R Berigei