Applied Materials, Inc.

Varian Semiconductor Equipment Associates, Inc.

Rajesh Prasad

Kyu-Ha Shim

Kwangduk Douglas Lee

Harry S Whitesell

Scott Falk

Deven Matthew Raj Mittal

Prashant Kumar Kulshreshtha

Sarah Michelle Bobek

Hidetaka Oshio

Venkataramana R Chavva

Min Gyu Sung

Steven Robert Sherman

Andrew Michael Waite

Somchintana Norasetthekul

Qi Gao

Tzu-Yu Liu

John J Hautala

Qintao Zhang

Sony Varghese

Tomohiko Kitajima

Nobuyuki Sasaki

Dong H Lee

Dong Hyung Lee

Deven Raj Mittal

Edwin A Arevalo

Kyuha Shim

Sungho Jo

Guy Oteri

Shan Tang

Ning Li

Srinivas D Nemani

Eric J Bergman

Karthik Janakiraman

Mihaela A Balseanu

Adolph Miller Allen

John Lee Klocke

Martin Jay Seamons

Jonathan Gerald England

Keith Tatseun Wong

Zhong Qiang Hua

Johannes M Van Meer

Terrance Y Lee

Chang Seok Kang

Shuaidi Zhang

Tom Ho Wing Yu

Jun-Feng Lu

Gautam K Hemani

Ning Zhan

Kurt Decker-Lucke

Adaeze Osonkie

Viabhav Soni

Ravi Rajagopalan

Lauren Liaw

Takaski Shimizu

Hurshvardhan Srivastava

Ryuichi Muira

Hans Gossmann

KyuHa Shim

Hiro Ito

James Cournoyer

Exemplary methods of semiconductor processing may include forming a layer of amorphous silicon on a semiconductor substrate. The layer of amorphous silicon may be characterized by a first amount of hydrogen incorporation. The methods may include performing a beamline ion implantation process or plasma doping process on the layer of amorphous silicon. The methods may include removing hydrogen from the layer of amorphous silicon to a second amount of hydrogen incorporation less than the first amount of hydrogen incorporation.

Ion implantation for reduced hydrogen incorporation in amorphous silicon

Methods for depositing a hardmask with ions implanted at different tilt angles are described herein. By performing ion implantation to dope an amorphous carbon hardmask at multiple tilt angles, an evenly distributed dopant profiled can be created. The implant tilt angle will determine a dopant profile that enhances the carbon hardmask hardness.

Forming a doped hardmask

A method of forming a semiconductor device may include forming a plurality of fins extending from a buried oxide layer, wherein a masking layer is disposed atop each of the plurality of fins, and performing a high-temperature ion implant to the semiconductor device. The method may further include performing an etch process to remove the masking layer from atop each of the plurality of fins, wherein the etch process does not remove the buried oxide layer.

Etch rate modulation of FinFET through high-temperature ion implantation

Methods of manufacturing memory devices are provided. The methods improve the quality of a selectively deposited silicon-containing dielectric layer. The method comprises selectively depositing a silicon-containing dielectric layer in a recessed region of a film stack. The selectively deposited silicon-containing dielectric layer is then exposed to a high-density plasma and annealed at a temperature greater than 800 ° C. to provide a silicon-containing dielectric film having a wet etch rate of less than 4 Å/min.

Sequential plasma and thermal treatment

Methods and techniques for deposition of amorphous carbon films on a substrate are provided. In one example, the method includes depositing an amorphous carbon film on an underlayer positioned on a susceptor in a first processing region. The method further includes implanting a dopant or the inert species into the amorphous carbon film in a second processing region. The implant species, energy, dose & temperature in some combination may be used to enhance the hardmask hardness. The method further includes patterning the doped amorphous carbon film. The method further includes etching the underlayer.

Highly etch selective amorphous carbon film

A method may include providing a substrate having, on a first surface of the substrate, a low dielectric constant layer characterized by a layer thickness. The method may include heating the substrate to a substrate temperature in a range of 200&#xb0; C. to 550&#xb0; C.; and directing an ion implant treatment to the low dielectric constant layer, while the substrate temperature is in the range of 200&#xb0; C. to 550&#xb0; C. As such, the ion implant treatment may include implanting a low weight ion species, at an ion energy generating an implant depth equal to 40% to 175% of the layer thickness.

Techniques for improved low dielectric constant film processing

A method to form a 2-Dimensional transistor channel may include depositing an amorphous layer comprising a 2-dimensional material, implanting an implant species into the amorphous layer; and annealing the amorphous layer after the implanting. As such, the amorphous layer may form a doped crystalline layer.

Method of forming a 2-dimensional channel material, using ion implantation

A system and method that allows higher energy implants to be performed, wherein the peak concentration depth is shallower than would otherwise occur is disclosed. The system comprises an ion source, an accelerator, a platen and a platen orientation motor that allows large tilt angles. The system may be capable of performing implants of hydrogen ions at an implant energy of up to 5 MeV. By tilting the workpiece during an implant, the system can be used to perform implants that are typically performed at implant energies that are less than the minimum implant energy allowed by the system. Additionally, the resistivity profile of the workpiece after thermal treatment is similar to that achieved using a lower energy implant. In certain embodiments, the peak concentration depth may be reduced by 3 &#x3bc;m or more using larger tilt angles.

System and technique for profile modulation using high tilt angles

A method of forming surface features in a hardmask layer, including etching a first surface feature into the hardmask layer, the first surface feature having a first critical dimension, performing an ion implantation process on the first surface feature to make the first surface feature resistant to subsequent etching processes, etching a second surface feature into the hardmask layer adjacent the first surface feature, wherein the first critical dimension is preserved.

Techniques for reducing tip to tip shorting and critical dimension variation during nanoscale patterning

A method may include depositing a carbon layer on a substrate using physical vapor deposition, wherein the carbon layer exhibits compressive stress, and is characterized by a first stress value; and directing a dose of low-mass species into the carbon layer, wherein, after the directing, the carbon layer exhibits a second stress value, less compressive than the first stress value.

Techniques for forming low stress etch-resistant mask using implantation

A method of forming a three-dimensional transistor device. The method may include providing a transistor structure, where the transistor structure includes a fin assembly, a gate assembly, the gate assembly disposed over the fin assembly and comprising a plurality of gates, a liner layer, disposed over the plurality of gates, and an isolation layer, disposed subjacent the liner layer. The method may also include directing first angled ions at the transistor device, wherein a first altered liner layer is created in the liner layer, wherein, in the presence of a liner-removal etchant, the liner layer exhibits a first etch rate, the first altered liner layer exhibits a second etch rate, greater than the first etch rate.

Techniques for forming dual epitaxial source/drain semiconductor device

Implementations described herein generally relate to the fabrication of integrated circuits. More particularly, the implementations described herein provide techniques for deposition of amorphous carbon films on a substrate. In one implementation, a method of forming an amorphous carbon film is provided. The method comprises depositing an amorphous carbon film on an underlayer positioned on a susceptor in a first processing region. The method further comprises implanting a dopant or inert species into the amorphous carbon film in a second processing region. The dopant or inert species is selected from carbon, boron, nitrogen, silicon, phosphorous, argon, helium, neon, krypton, xenon or combinations thereof. The method further comprises patterning the doped amorphous carbon film. The method further comprises etching the underlayer.

A method may include providing a substrate, comprising a patterning layer. The method may include forming a first pattern of first linear structures in the patterning layer, the first linear structures being elongated along a first direction. The method may include forming a mask over the patterning layer, the mask comprising a second pattern of second linear structures, elongated along a second direction, forming a non-zero angle with respect to the first direction. The method may include selectively removing a portion of the patterning layer while the mask is in place, wherein a first etch pattern is formed in the patterning stack, the first etch pattern comprising a two-dimensional array of cavities. The method may include directionally etching the first etch pattern using an angled ion beam, wherein a second etch pattern is formed, comprising the two-dimensional array of cavities, elongated along the first direction.

Techniques and structure for forming dynamic random-access device using angled ions

Growing community of inventors

Lexington, MA, United States of America

Rajesh Prasad