Intel Corporation

Rajesh Galivanche

Sandip Kundu

Sanjay Sengupta

Srinivas Patil

Abhijit Jas

Ramtilak Vemu

A method, apparatus and system for accepting a plurality of user-selected properties pre-designated for detecting errors in portions of a circuit, accepting a plurality of user-selected erroneous outputs, each of which may correspond to one of the plurality of user-selected set of properties, executing a simulation of the circuit for each of the plurality of user-selected properties, detecting in the output of the simulation, one of the plurality of user-selected erroneous outputs of the circuit for the corresponding one of the plurality of user-selected properties, and performing error correction on the circuit for the corresponding one of the plurality of user-selected properties. A method, apparatus and system for automatically selecting a subset of a set of inputs which when input into a circuit simulation generate erroneous output data to a primary output of the circuit and performing error correction on the circuit therewith. Other embodiments are described and claimed.

Device, system, and method for optimized concurrent error detection

A packaged component includes a pattern generator for generating successive random data patterns. The component further includes a programmable constraint correction module, coupled to the pattern generator, to replace undesirable random data patterns with desirable bit sequences to overcome bus contention problems in the generated random data patterns. The component further includes an integrated circuit device to be functionally tested. The device receives the constrained random data patterns from the constraint correction module and outputs a test result. The device further includes a programmable X-masking module coupled to the device receives and masks the test result by replacing unpredictable bit values in the received test result with predictable bit values. A signature analyzer coupled to the X-masking module receives the masked test result and compresses the test result into a signature. Then a comparator coupled to the signature analyzer compares the signature with a predetermined test result to determine whether the device is free of structural defects.

Dft technique for avoiding contention/conflict in logic built-in self-test

A test system for structurally testing an integrated circuit device includes a pattern generator for generating successive random data patterns (scan chain). The test system further includes a constraint checker and corrector module, coupled to the pattern generator, to replace undesirable random data patterns (state elements joined together in the scan chain such that one state element is connected to a ground and the other state element is connected to a power supply) with desirable bit sequences to eliminate bus contention problems in the generated random data patterns. The test system further includes the integrated circuit device to be tested. The integrated circuit device receives the constrained random data patterns from the constraint checker and corrector module and outputs a test result. The test system further includes an X-masking module coupled to the integrated circuit device. The X-masking module receives the test result from the integrated circuit device, and it masks the test result by replacing unpredictable bit values (these are bit values generated due to not scanning some state elements in the scan chain) in the test result with predictable bit values. A signature analyzer coupled to the X-masking module receives the masked test result and compress the test result into a signature. Then a comparator coupled to the signature analyzer compares the signature with a predetermined test result to determine the functionality of the integrated circuit device.

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Sunnyvale, CA, United States of America

Rajesh Galivanche