Texas Instruments Corporation

Rajesh B Khamankar

Haowen Bu

Douglas Ticknor Grider

Hiroaki Niimi

Husam N Alshareef

April Gurba

Brian Keith Kirkpatrick

Malcolm John Bevan

Sunil V Hattangady

Mark R Visokay

James Joseph Chambers

Mark H Somervell

Clinton L Montgomery

Luigi Colombo

Antonio L P Rotondaro

Srinivasan Chakravarthi

Pr Chidambaram

Ajith Varghese

Toan Tran

Che-Jen Hu

Scott Robert Summerfelt

Freidoon Mehrad

Shashank Sureshchandra Ekbote

Guoqiang Xing

Akitoshi Nishimura

Shaoping Tang

Periannan Chidambaram

Shane R Palmer

Yasutoshi Okuno

Douglas E Mercer

P R Chidambaram

Jaideep Mavoori

Rick L Wise

Lindsey H Hall

Darius Lammont Crenshaw

Anand T Krishnan

Eddie Hearl Breashears

Mark A Kressley

Katherine E Violette

Mercer Brugler

Jon Holt

Aditi D Banerjee

Cathy A Chancellor

Sung-Jen Fang

Corbett Zabierek

A silicon nitrate layer () is formed over a transistor gate () and source and drain regions (). The as-formed silicon nitride layer () comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer () is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer () is greater than 12 atomic percent.

High performance CMOS transistors using PMD liner stress

An integrated circuit containing a PMOS transistor with p-channel source/drain (PSD) regions which include a three layer PSD stack containing Si&#x2014;Ge, carbon and boron. The first PSD layer is Si&#x2014;Ge and includes carbon at a density between 5&#xd7;10and 2&#xd7;10atoms/cm. The second PSD layer is Si&#x2014;Ge and includes carbon at a density between 5&#xd7;10atoms/cmand 2&#xd7;10atoms/cmand boron at a density above 5&#xd7;10atoms/cm. The third PSD layer is silicon or Si&#x2014;Ge, includes boron at a density above 5&#xd7;10atoms/cmand is substantially free of carbon. After formation of the three layer epitaxial stack, the first PSD layer has a boron density less than 10 percent of the boron density in the second PSD layer. A process for forming an integrated circuit containing a PMOS transistor with a three layer PSD stack in PSD recesses.

In-situ carbon doped e-SiGeCB stack for MOS transistor

Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than single layer PMD liners. Each layer in the inventive PMD liner is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 1300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instability (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed.

Laminated stress overlayer using In-situ multiple plasma treatments for transistor improvement

A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation. The enhanced yield strength of the substrate mitigates plastic deformation of the transistor due to the strain inducing layer.

Nitrogen based implants for defect reduction in strained silicon

Semiconductor devices () and fabrication methods () are provided, in which a nitride film () is formed over NMOS transistors to impart a tensile stress in ail or a portion of the NMOS transistor to improve carrier mobility. The nitride layer () is initially deposited over the transistors at low temperature with high hydrogen content to provide a moderate tensile stress in the semiconductor body prior to back-end processing. Subsequent back-end thermal processing reduces the film hydrogen content and causes an increase in the applied tensile stress.

PMD liner nitride films and fabrication methods for improved NMOS performance

A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition.

Gate structure and method

A method () of forming semiconductor structures () including high-temperature processing steps (step), incorporates the use of a high-temperature nitride-oxide mask () over protected regions () of the device (). The invention has application in many different embodiments, including but not limited to, the formation of recess, strained device regions ().

Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps

A method of reducing threshold voltage shift of a MOSFET transistor resulting after temperature and voltage stress, and an integrated circuit device fabricated according to the method. The method includes the steps of forming a nitrided dielectric layer on a semiconductor substrate, and subjecting the nitrided dielectric layer to an anneal at low pressure.

Thermal treatment of nitrided oxide to improve negative bias thermal instability

The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite cap to alter the active dopant profile across the channel regions. During an annealing process, dopants migrate out of the Si/SiO2 in a channel region thereby altering the dopant profile of the channel region. This altered profile generally improves channel mobility thereby improving transistor performance and permitting smaller density designs.

Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance

Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer () is formed on a semiconductor substrate (). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer () is removed in regions of the substrate and a second dielectric layer () is formed in these regions. A second plasma nitridation process is performed on the first dielectric layer and the second dielectric layer. MOS transistors () are then fabricated using the dielectric layers ().

Reliable high voltage gate dielectric layers using a dual nitridation process

The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semiconductor (PMOS) device () having a first gate dielectric layer () and a first gate electrode layer () located over a substrate (), wherein the first gate dielectric layer () has an amount of nitrogen located therein. In addition to the PMOS device (), the CMOS device further includes an n-channel metal oxide semiconductor (NMOS) device () having a second gate dielectric layer () and a second gate electrode layer () located over the substrate (), wherein the second gate dielectric layer () has a different amount of nitrogen located therein. Accordingly, the present invention allows for the individual tuning of the threshold voltages for the PMOS device () and the NMOS device ().

CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers

The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.

Post high voltage gate oxide pattern high-vacuum outgas surface treatment

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Irving, TX, United States of America

Rajesh B Khamankar