Fairchild Semiconductor Corporation

Texas Instruments Corporation

National Semiconductor Corporation

Flextronics Ap, LLC

Fairchild Korea Semiconductor Ltd.

Other

Fiarchild Semiconductor

Rajeev Dinkar Joshi

Chung-Lin Wu

Consuelo N Tangpuz

Jonathan A Noquil

Venkat Iyer

Romel Nogas Manatad

Maria Cristina B Estacio

Anindya Poddar

Erwin Victor R Cruz

Oseob Jeon

Margie T Rios

Boon Huan Gooi

Yoonhwa Choi

Connie Tangpuz

Seung Yong Choi

Byoung-Ok Lee

Sreenivasan Kalyani Koduri

Yogesh Kumar Ramadass

Jeffrey Anthony Morroni

Ken Pham

Hau Thanh Nguyen

Roberto Giampiero Massolini

Sujan Kundapur Manohar

Joyce Marie Mullenix

Jonathan Klein

David Chong

Lay Yeap Lim

Honorio T Granada, Jr

Tan Teik Keng

Shibaek Nam

Jaime A Bayan

Steven Paul Sapp

Ashok S Prabhu

Ji Hwan Kim

O-seob Jeon

Maria Clemens Y Quinones

Stephen Martin

Shi-baek Nam

Yoon-hwa Choi

Jie Mao

Min Hyo Park

A semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and a passive component electrically connected to the semiconductor die through the leadframe. The leadframe includes a cavity in a side of the leadframe opposite the semiconductor die, and at least a portion of the passive component resides within the cavity in a stacked arrangement.

Integration of a passive component in a cavity of an integrated circuit package

A method includes forming a first magnetic material on a first surface of a conductive loop, forming a second magnetic material on a second surface of the conductive loop opposite the first surface to form an inductor, attaching a semiconductor die to a leadframe, and attaching the inductor to the leadframe with solder balls. The semiconductor die is between the inductor and the leadframe. The conductive loop: spans parallel to the leadframe; or is between the first magnetic material and the second magnetic material.

Semiconductor package with integrated passive electrical component

A semiconductor package includes a leadframe and a semiconductor die attached to the leadframe by way of solder posts. In a stacked arrangement, the package also includes a passive component disposed between the leadframe and the semiconductor die and electrically connected to the semiconductor die through the leadframe.

Integration of a passive component in an integrated circuit package

A semiconductor package includes a leadframe comprising input/output pins accessible external to the semiconductor package and a semiconductor die electrically connected to the leadframe. The semiconductor package also includes a passive electrical component mounted on a side of the semiconductor die opposite the leadframe. Mold compound encapsulates the passive electrical component, semiconductor die, and leadframe to form the semiconductor package. Associated methods are disclosed as well.

A power supply module includes a metallic clip including a plate having an area and a first and a second ridge on opposite sides of the plate. The ridges bent in the same direction away from the plate. The first and the second ridges conductively attached to the substrate, where the substrate is of insulating material integral with metal traces, the plate roofing over the substrate between the ridges. A first MOS field-effect transistor (FET) chip and, horizontally side-by-side, a second MOSFET chip are attached and wire bonded to the substrate under the plate. The drain of the first MOSFET is connected to the input terminal of the module, the source of the first MOSFET is tied to the drain of the second MOSFET, and the source of the second MOSFET, together with the second ridge, is connected to ground. A driver and controller chip is attached to the substrate under the plate and wire bonded to the gates of the first and second MOSFET. A capacitor is attached to the substrate under the clip plate and conductively connected to the first clip ridge and to the drain of the first MOSFET.

Power converter having a conductive clip

A dual leadframe () for semiconductor systems comprising a first leadframe () having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe () having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions () in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material () filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.

Semiconductor systems having dual leadframes

Semiconductor systems having premolded dual leadframes

Disclosed examples include power modules and fabrication methods therefor in which one or more power device dies include a switching device and a second device die with a circuit component are mounted to a lead frame or other interconnect structure on a substrate structure, and a body structure is formed around portions of the power module providing a first opening to expose a portion of the substrate structure to provide an externally accessible first exposed surface along the top of the power module, and the body structure includes a second opening exposing a portion of the first device die along the bottom of the power module to provide a thermally conductive path to draw heat away from the power device dies.

Power module with improved cooling and method for making

Power supply system comprises vertically sequentially a QFN leadframe, a first chip with FET terminals on opposite sides, a flat interposer, and a second chip with FET terminals and the terminals of the integrated driver-and-control circuit on a single side. Leadframe pad has a portion recessed as pocket with a depth and an outline suitable for attaching the first chip with one terminal in the pocket and the opposite terminal co-planar with the un-recessed pad surface. The interposer comprises metal patterned in traces separated by gaps; the traces include metal of a first height and metal of a second height smaller than the first height, and insulating material filling the gaps and the height differences; one interposer side attached to the leadframe pad with the first chip, the opposite interposer side attached to the terminals of the second chip.

Converter having partially thinned leadframe with stacked chips and interposer, free of wires and clips

Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Semiconductor die package and method for making the same

Power supply system () comprises vertically sequentially a QFN leadframe (), a first chip () with FET terminals on opposite sides, a flat interposer (), and a second chip () with FET terminals and the terminals of the integrated driver-and-control circuit on a single side. Leadframe pad () has a portion () recessed as pocket with a depth and an outline suitable for attaching the first chip with one terminal in the pocket and the opposite terminal co-planar with the un-recessed pad surface. The interposer comprises metal patterned in traces separated by gaps; the traces include metal of a first height and metal of a second height smaller than the first height, and insulating material filling the gaps and the height differences; one interposer side attached to the leadframe pad with the first chip, the opposite interposer side attached to the terminals of the second chip.

Embodiments of the present invention relate to a method of forming a magnetics package. The method includes providing a primary coil configured to conduct a current flow; providing a substrate having a surface and a secondary coil extending from the surface, the secondary coil configured to conduct a current flow; encapsulating the secondary coil in a secondary mold compound; removing the substrate from the secondary coil, thereby leaving the secondary coil embedded in the secondary mold compound; and inductively coupling the secondary coil to the primary coil through a magnetic core, the secondary coil is electrically isolated from the primary coil, wherein a current flow in the primary coil produces a magnetic field in the magnetic core, and the magnetic field in the magnetic core induces a current flow in the secondary coil.

Method of forming a magnetics package

Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.

DC/DC converter power module package incorporating a stacked controller and construction methodology

A leadframe based photovoltaic assembly and method for assembling the same is disclosed. The photovoltaic assembly comprises a first and second mold compounds to effectuate the accurate placement of an optical concentrator above a photovoltaic cell. The photovoltaic assembly is able to be assembled using existing mature semiconductor packaging technologies.

Leadframe based photo voltaic electronic assembly

Growing community of inventors

Cupertino, CA, United States of America

Rajeev Dinkar Joshi