International Business Machines Corporation

Micron Technology Incorporated

Adeia Semiconductor Bonding Technologies Inc.

Globalfoundries Inc.

Tessera LLC

Rajasekhar Venigalla

Reinaldo Ariel Vega

Hari V Mallela

Bruce Bennett Doris

Andrew Mark Greene

Robert Russell Robison

Hong He

Chia-Yu Chen

Brent A Anderson

Dechao Guo

Ravikumar Ramachandran

Seong-Dong Kim

Marc Adam Bergendahl

Michael A Guillorn

Sivananda K Kanakasabapathy

Ruqiang Bao

David Lee Rath

Viraj Yashawant Sardesai

Kisup Chung

Kevin Lee Baker

Efe Sinan Ege

Indira P V Seshadri

Tenko Yamashita

Oleg Gluschenkov

Balasubramanian Pranatharthiharan

Terence B Hook

Praneet Adusumilli

Zuoguang Liu

Kafai Lai

Su Chen Fan

Unoh Kwon

Hiroyuki Miyazoe

Emre Alptekin

Michael P Belyansky

Cung D Tran

Amitava Majumdar

Jian Yu

Pengyuan Zheng

Radhakrishna Kotti

Lei Wei

Patrick M Flynn

Dong-Ick Lee

Tao D Nguyen

Josiah Jebaraj Johnley Muthuraj

Timothy M McCormack

Adam Thomas Barton

Davis Weymann

Kangguo Cheng

Jordan D Greenlee

Laertis Economikos

John Ryan Sporre

Huiming Bu

Albert Manhee Chu

Gauri V Karve

Henry K Utomo

Stuart A Sieg

Nancy M Lomeli

Huimei Zhou

Rishikesh Krishnan

Gen Tsutsui

Michael Vincent Aquilino

Christopher D Sheraw

Daewon Yang

Alan C Thomas

James Hannah

Tom George

Robert M Merkling, Jr

Marc A Bergendahl

Andrew M Greene

Glenn L Cellier

Massud A Aminpur

Dimitri Anastassios Levedakis

A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers directly above a conductor tier that comprises silicon-containing material. The stack comprises laterally-spaced memory-block regions and a through-array-via (TAV) region. The stack comprises channel-material strings that extend through the first tiers and the second tiers in the memory-block regions. The stack comprises TAV openings in the TAV region that extend to the silicon-containing material of the conductor tier. A metal halide is reacted with the silicon of the silicon-containing material to deposit the metal of the metal halide in the conductor tier. After depositing the metal, conductive material is formed in the TAV openings directly against the deposited metal and therefrom a TAV is formed in individual of the TAV openings that comprises the conductive material and the deposited metal. Structure embodiments are disclosed.

Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. A through-array-via (TAV) region comprises TAVs that individually extend through the insulative tiers and the conductive tiers into the conductor tier. Individual of the TAVs comprise an upper portion directly above and joined with a lower portion. The individual TAVs comprise at least one external jog surface in a vertical cross-section where the upper and lower portions join. The lower portion is wider in the vertical cross-section than the upper portion where the upper and lower portions join. Other embodiments, including method, are disclosed.

A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.

Gate cut with integrated etch stop layer

Methods, systems, and devices supporting a socket design for a memory device are described. A die may include one or more memory arrays, which each may include any number of word lines and any number of bit lines. The word lines and the bit lines may be oriented in different directions, and memory cells may be located at the intersections of word lines and bit lines. Sockets may couple the word lines and bit lines to associated drivers, and the sockets may be located such that memory cells farther from a corresponding word line socket are nearer a corresponding bit line socket, and vice versa. For example, sockets may be disposed in rows or regions that are parallel to one another, and which may be non-orthogonal to the corresponding word lines and bit lines.

Socket design for a memory device

Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. The manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. The manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.

Low resistance crosspoint architecture

A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.

Memory with optimized resistive layers

A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.

Nanosheet field effect transistors with partial inside spacers

An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in an first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner.

Additive core subtractive liner for metal cut etch processes

An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in a first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner.

Growing community of inventors

Hopewell Junction, NY, United States of America

Rajasekhar Venigalla