Infineon Technologies Ag

Other

International Business Machines Corporation

Qimonda Ag

Rainer Florian Schnabel

Johann Pfeiffer

Roy Charles Iggulden

Stefan Weber

Lawrence Alfred Clevenger

Jeffrey P Gambino

Kenneth Parker Rodbell

Ronald G Filippi

Helmut Schneider

Ulrike Gruening

Gerhard Mueller

Michael Bernhard Sommer

Helmut Fischer

Chao-Kun Hu

Lynne Marie Gignac

Volker Weinrich

Gerhard Beitel

Thomas S Rupp

Larry Clevenger

Guenther Schindler

Annette Saenger

Andreas Thies

Barbara Hasler

Sirko Kramp

Gerd Mainka

An integrated circuit comprises a first conductive lines and second lines as well as contact structures being in contact with the first and second conductive lines. The first conductive lines are arranged in a first metallization level, and second conductive lines are arranged in a second metallization level arranged above the first metallization level. The second conductive lines are arranged above the contact structures, and a pitch of neighboring contact structures is equal to a pitch of neighboring second conductive lines. The distance between neighboring contact structures is smaller than 100 nm.

Integrated circuit comprising conductive lines and contact structures and method of manufacturing an integrated circuit

The source area () is highly doped, like the channel area, for the same conductance type. The drain area () is doped for the opposite conductance type. This results in a saving of area since the source connection (S) can at the same time be used as the well connection or substrate connection.

Semiconductor component with a MOS transistor

The invention relates to a method for reducing the current consumption of an electronic circuit having at least one test module for testing the electronic circuit. The test module is connected to at least one line and/or a connection of the electronic circuit. A test control signal is generated, by means of which the test module is at least partially decoupled from the line or the connection in an operating mode of the electronic circuit such that switching currents are prevented in the test module.

Method and apparatus for reducing the current consumption of an electronic circuit

The invention discloses a method for the chemical-mechanical polishing of layers composed of metals of the group of platinum metals, particularly iridium. In the CMP process, high erosion rates for iridium and a high selectivity relative to silicon oxide are achieved upon employment of a polishing fluid that contains 1 through 6% by weight abrasive particles, 2 through 20% by weight of at least one oxidation agent selected from the group comprising Ce(IV) salts, salts of chloric acid, salts of peroxodisulfuric acid, hydrogen peroxide and salts of hydrogen peroxide, and 74 through 97% by weight water. This enables the structuring of iridium layers with the assistance of an oxide mask and a CMP process.

Method for chemical-mechanical polishing of a layer which is a substrate and is a metal selected from a platinum group

The integrated circuit has a test circuit, which is connected to an input terminal of the integrated circuit via a line connection. An isolating device is provided between an input terminal of the test circuit in order to completely isolate the line connection between the test circuit and the input terminal after the test circuit has performed a test procedure.

Integrated circuit having a test circuit, and method of decoupling a test circuit in an integrated circuit

It is an aim to reduce an area required on a chip for interconnects which cross a spine center. The circuit has n inputs, which are disposed on one side of the spine center. An encoder is additionally provided, which is connected to the n inputs on an input side and to one end of the interconnects on an output side and which is likewise disposed on one side of the spine center. In this case, a number n of the inputs is greater than a number of the interconnects. A decoder, which is connected to the other end of the interconnects on the input side and to n outputs on the output side, is disposed on the other side of the spine center.

Circuit for an electronic semiconductor module

A method is described for producing a conducting connection through insulating layers by way of a contact hole and conducting materials with which the contact hole is filled. The method permits the production of a contact hole resembling the shape of a wineglass, into which conducting filling material and barrier layers can be inserted without the known problems such as void formation, overetching trenches, and dielectric close-off. It is possible in this way, for example, to produce an electric connection between the diffusion zone of a selection transistor and the lower electrode of a storage capacitor of large-scale integrated DRAM and FeRAM components with the aid of only a few mask steps.

Method for producing an electrically conducting connection

A dual damascene process capable of reliably producing aluminum interconnects that exhibit improved electromigration characteristics over aluminum interconnects produced by conventional RIE techniques. In particular, the dual damascene process relies on a PVD-Ti/CVD-TiN barrier layer to produce aluminum lines that exhibit significantly reduced saturation resistance levels and/or suppressed electromigration, particularly in lines longer than 100 micrometers. The electromigration lifetime of the dual damascene aluminum line is strongly dependent on the materials and material fill process conditions. Significantly, deviations in materials and processing can result in electromigration lifetimes inferior to that achieved with aluminum RIE interconnects. In one example, current densities as high as 2.5 MA/cm are necessary to induce a statistically relevant number of fails due to electromigration.

Aluminum-based metallization exhibiting reduced electromigration and method therefor

A method is provided in which intermediate sized structures can be filled without forming voids during the fill process. The methods involve use of a sequence of CVD/PVD/CVD/PVD steps. The methods are especially effective for filling &ldquo;intermediate&rdquo; size features in damascene and dual damascene structures.

CVD/PVD/CVD/PVD fill process

A method for fabricating a semiconductor memory with a split level folded bitline structure consisting of three contact levels, in accordance with the present invention includes forming gate structures for transistors in an array region and a support region of a substrate. First contacts are formed down to diffusion regions between the gate structures in the array region. The first contacts have a height which is substantially the same for all first contacts in the array region. Second contacts are formed between first level bitlines in the array region and a first portion of the first contacts, while forming second contacts to a first metal layer from the gate structures and diffusion regions in the support region. Third contacts are formed between second level bitlines in the array region and a second portion of the first contacts, while forming third contacts to a second metal layer from the first metal layer in the support region.

Growing community of inventors

Hoehenkirchen, Germany

Rainer Florian Schnabel