Siemens Aktiengesellschaft

International Business Machines Corporation

Infineon Technologies LLC

Rainer F Schnabel

Jeffrey P Gambino

Mark A Jaso

Xian J Ning

Jack Allan Mandelman

Carl John Radens

Gary Bela Bronner

Chandrasekhar Narayan

Ronald J Schutz

Dirk Tobben

Kenneth C Arndt

Zhijian Lu

Virinder Grewal

Greg Costrini

Bruno Spuler

Bernd M Vollmer

Klaus Feldner

A method and apparatus is provided for planarizing damascene metallic circuit patterns of a plurality of discrete integrated circuit chips on a metal coated silicon wafer wherein the circuitry on the chips on the wafer are either designed to be within a defined high metal density circuit range and low density metal circuit range and/or to provide dummy circuitry in the damascene process to provide a substantially uniform circuit density over the chip and the wafer surface. It is preferred that each chip on the surface of the wafer be divided into a plurality of regions and that each region be provided with dummy metallization, if necessary, to provide a relatively uniform circuit density in that region and consequently on the wafer surface. The invention also contemplates adding dummy circuitry to the periphery of the wafer in areas which are not formed into chips (chip fragments). The invention also provides semiconductor wafers made using the method and/or apparatus of the invention.

Dummy patterns for aluminum chemical polishing (CMP)

An improved method of performing a dual damascene etch through a layer stack disposed above a substrate. The layer stack includes an underlying device layer and an insulating layer disposed above the underlying device layer. The method includes forming a trench in a top surface of the insulating layer such that the trench is positioned over the underlying device layer and separated therefrom by insulating material at a bottom of the trench. The method also includes, depositing flowable oxide over the top surface of the insulating layer and into the trench followed by planarizing the flowable oxide down to about a level of the top surface of the insulating layer. Further, the method includes, etching through the flowable oxide within the trench and through insulating material at the bottom of the trench down to the underlying device layer to form a via.

Method of forming multi-level coplanar metal/insulator films using dual damascene with sacrificial flowable oxide

A process of forming a wiring in a semiconductor interlayer dielectric, include simultaneously patterning a via and a slotted line in the interlayer diectric, simultaneously etching the via and the slotted line, and simultaneously filling the via and the slotted line with a metal.

Slotted damascene lines for low resistive wiring lines for integrated circuit

A method for forming self-aligned features for semiconductor devices includes the steps of providing a first layer including a reflective material on a surface of the first layer, a second layer formed on the first layer, and a resist layer formed on the second layer, providing radiation through the resist layer and the second layer wherein the radiation is reflected from the reflective material back to the resist layer thereby increasing irradiation of the resist layer over the reflective material and developing the resist layer. A semiconductor device in accordance with the invention includes a first layer with reflective structures therein. A second layer is formed on the first layer, and a patterned resist layer is formed on the second layer. Etched holes are formed in the second layer in accordance with the resist layer pattern, and interconnects are formed in the holes for electrically coupling to the reflective structures wherein the patterned resist layer is rendered by light transmitted through the resist layer and the second layer and reflected from the reflective structures thereby adequately exposing areas directly over the reflective structures, the exposed areas defining the interconnect locations such that the interconnects are aligned with the reflective structures when formed in the holes.

Self-aligned formation and method for semiconductors

A method for optically measuring layer thickness in accordance with the present invention includes the steps of providing a first metal layer on a semiconductor device structure, providing a second metal layer on the first metal layer, forming a dielectric layer over the second metal layer and directing light onto the structure such that light reflected from a surface of the dielectric layer and a surface of the second metal layer create an interference pattern from which the dielectric layer thickness is measured. A system for optically measuring layer thickness includes a semiconductor device to be measured. The semiconductor device includes a first metal layer, a second metal layer disposed on the first metal layer, the second metal layer having an arcuate shaped top surface and a dielectric layer disposed on the second metal layer. A means for directing and receiving light is also included wherein light is directed onto the semiconductor device such that light reflected from a surface of the dielectric layer and a surface of the second metal layer creates an interference pattern from which the dielectric layer thickness is measured.

System and methods for optically measuring dielectric thickness in

A semiconductor structure comprising a semiconductor substrate, an electrically conductive level on the substrate and a metal fuse located at the conductive level wherein the fuse comprises a self-aligned dielectric etch stop layer thereon is provided along with processes for its fabrication.

Semiconductor structure including a conductive fuse and process for

An improved method of forming a bond pad (222) by performing a dual damascene etch through a layer stack (200) disposed above a substrate (204) using self aligned vias (216). The layer (200) stack includes an underlying conductive layer (208) and an insulating layer (202) disposed above the underlying conductive layer (208). The method includes the following operative steps. At least a via hole (216) is formed in the insulating layer (202) positioned over the underlying device layer (208) and extending to the underlying device layer (208) at the bottom of the via hole. A bond pad trench (218) is then formed that takes the form of the desired bond pad (222). A layer of conductive material (220) is then placed over the insulating layer (202) substantially simultaneously filling the via hole (216) and the bond pad trench (218). The bond pad (222) is then formed by removing the layer of conductive material (220) sufficient to expose the upper surface of the insulating layer (210).

Dual damascene with bond pads

Methods for detecting under-etched vias, spaces, or under-polished portions in a wafer stack are disclosed. The wafer stack comprises a dielectric layer disposed on a metal layer. The dielectric layer has a plurality of vias etched therein. The wafer stack, including the plurality of vias, is exposed to an etchant which is configured to etch the metal layer at a substantially faster rate than the dielectric layer. As a result, cavities are formed in the metal layer below properly-etched vias. Then, the vias in the wafer stack are optically inspected to detect and identify under-etched vias, which reflect more light than the cavities etched into the metal layer.

Growing community of inventors

Wappingers Falls, NY, United States of America

Rainer F Schnabel