Intel Corporation

Rahul N Manepalli

Srinivas V Pietambaram

Gang Duan

Kristof Darmawikarta

Suddhasattwa Nad

Marcel Arlan Wall

Robert Alan May

Dingying David Xu

Yosuke Kanaoka

Wei-Lun Kane Jen

Xiaoying Guo

Jesse Jones

Robert L Sankman

Debendra Mallik

Saikumar Jayaraman

Sri Ranga Sai Boyapati

Kyu Oh Lee

Rahul Jain

Javier Soto Gonzalez

Tarek A Ibrahim

Aleksandar Aleksov

Nachiket R Raravikar

Yonggang Li

Leonel R Arana

Amruthavalli Pallavi Alur

Dilan Seneviratne

Sai Vadlamani

Siddharth K Alur

Deepak Kulkarni

Vipul V Mehta

Mohit Mamodia

Sri Chaitra J Chavali

Jung Kyu Han

Darko Grujicic

Ashish Dhall

Digvijay Ashokkumar Raorane

Rajasekaran Swaminathan

Bai Nie

Jason M Gamba

Hongxia Feng

Srinivas Venkata Ramanuja Pietambaram

Roy Dittler

Hong Dong

Shinobu Kourakata

Kemal Aygun

Sairam Agraharam

Edward Rudolph Prack

Choong Kooi Chee

Nisha Ananthakrishnan

Steve S Cho

Praneeth Kumar Akkinepally

Ravindra V Tanikella

Paul R Start

Gregory S Constable

Rengarajan Shanmugam

Cemil S Geyik

Saravanan Krishnan

Karen Y Paghasian

Ruel D R Aranda

Vishal Shajan

Telesphor Kamgaing

Omkar G Karhade

John Stephen Guzek

Ravindranath Vithal Mahajan

Nitin A Deshpande

Islam A Salama

Jeremy D Ecton

Yikang Deng

Junnan Zhao

Pramod Malatkar

Hiroki Tanaka

Edvin Cetegen

Chong Zhang

Stephen Edward Lehman, Jr

Sri Chaitra Jyotsna Chavali

Sandeep Razdan

Tian-An Chen

Hamid Azimi

Amram Eitan

Changhua Liu

Frank Truong

Bharat P Penmecha

Drew W Delaney

Kousik Ganesan

Terry Lee Sterrett

Meizi Jiao

Matthew L Tingey

Sameer Paital

Baris Bicen

Haobo Chen

Vassoudevane Lebonheur

Sandeep Gaan

David Unruh

David Q Xu

Adrian Bayraktaroglu

Marcel A Wall

Yue Deng

Kyle Mcelhinny

Maroun D Moussallem

Nisha Ananthakrisnan

A computer apparatus includes a hierarchy of solder joints in a multi-chip package, with solder joints at different levels of the packaging having different melting temperatures. Interconnections, such as pads or pins, on integrated circuit (IC) die can be electrically coupled to ends of contact pillars with solder joints having a higher melting temperature. The other ends of the contact pillars can electrically couple to another substrate or another device with solder joints having a lower melting temperature. The contact pillars can be, for example, a contact array or through-hole via in a substrate.

Solder interconnect hierarchy for heterogeneous electronic device packaging

The present disclosure is directed to an electroless plating process using a panel basket for holding semiconductor panels comprising a plurality of metal pads and shielding the metal pads from contaminants and over-etching and under-etching caused by the contaminants.

Electroless plating process

Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes bumps to electrically couple the die to the substrate. Ones of the bumps have corresponding bases. The bases have a shape that is non-circular.

Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates

An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

Package with underfill containment barrier

Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

Chiplet first architecture for die tiling applications

A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.

Inorganic-based embedded-die layers for modular semiconductive devices

An electronic substrate may be fabricated to include a fine pitch dielectric layer having an upper surface, a coarse pitch dielectric layer on the upper surface of the fine pitch dielectric layer, and at least one hybrid conductive via extending through the fine pitch dielectric layer and the coarse pitch dielectric layer. The hybrid conductive via is fabricated such that a portion thereof that extends through the fine pitch dielectric layer is smaller than a portion extending through the coarse pitch dielectric layer, which results in a stepped configuration, wherein a portion of the hybrid conductive via abuts the upper surface of the fine pitch dielectric layer. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate, such that the bridge provides device-to-device interconnection therebetween.

Hybrid conductive vias for electronic substrates

An electronic package includes an interposer having an interposer substrate, a cavity that passes into but not through the interposer substrate, a through interposer via (TIV) within the interposer substrate, and an interposer pad electrically coupled to the TIV. The electronic package includes a nested component in the cavity, wherein the nested component includes a component pad coupled to a through-component via. A core via is beneath the nested component, the core via extending from the nested component through the interposer substrate. A die is coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect.

Nested interposer with through-silicon via bridge die

An electronic substrate may be formed having at least one metal-to-dielectric adhesion promotion material layer therein. The electronic substrate may comprise a conductive metal trace, a dielectric material layer on the conductive metal trace, and the adhesion promotion material layer between the conductive metal trace and the dielectric material layer, wherein the adhesion promotion material layer comprises an organic adhesion material and a metal constituent dispersed within the organic adhesion material, wherein a metal within the metal constituent has a standard reduction potential greater than a standard reduction potential of the conductive metal trace.

Dielectric-to-metal adhesion promotion material

Electrical interconnect bridge technology is disclosed. An electrical interconnect bridge can include a bridge substrate formed of a mold compound material. The electrical interconnect bridge can also include a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and space (FLS) traces. In addition, the electrical interconnect bridge can include a via extending through the substrate and electrically coupling at least one of the FLS traces in one of the routing layers to at least one of the FLS traces in another of the routing layers.

Electrical interconnect bridge

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.

Hybrid fan-out architecture with EMIB and glass core for heterogeneous die integration applications

Microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.

Embedded die microelectronic device with molded component

Embodiments disclosed herein include electronic packages and methods of making electronic packages. In an embodiment, the electronic package comprises a package substrate, an array of first level interconnect (FLI) bumps on the package substrate, wherein each FLI bump comprises a surface finish, a first pad on the package substrate, wherein the first pad comprises the surface finish, and wherein a first FLI bump of the array of FLI bumps is electrically coupled to the first pad, and a second pad on the package substrate, wherein the second pad is electrically coupled to the first pad.

Sacrificial pads to prevent galvanic corrosion of FLI bumps in EMIB packages

Growing community of inventors

Chandler, AZ, United States of America

Rahul N Manepalli