Advanced Micro Devices Corporation

Palantir Technologies Inc.

Tc1 LLC

Ati Technologies Ulc

Numenta, Inc.

Kinetic Technologies

Megachips Technology America Corporation

Other

Boomi, Inc.

Advances Micro Devices, Inc.

Rahul Kumar Agarwal

Milind S Bhagavat

Brett P Wilkerson

Daniel Erenrich

Aleksandr Zamoshchin

Lei Fu

Matthew Elkherj

Lawrence Manning

Xavier Falco

Eli Bingham

Yifei Huang

Priyal Shah

Roger Hu

Daniel Fernandez

Guillem Palou Visa

Jeremy Elser

Rahul Mehta

Clayton Sader

Nicholas Latourette

Rowan Gilmore

Jason Prestinario

Gabriel H Loh

Alan Osamu Kobayashi

Ramakrishna Chilukuri

Raja Swaminathan

Diane Wu

Sujan Valiyaka Thomas

Chia-Hao Cheng

Yelena Nabutovsky

Ivor G Barber

Andre Frederico Cavalheiro Menck

David Lisuk

Guodong Xu

Anirvan Mukherjee

Simon Slowik

Julie Prillinger

Luis Voloch

Daniel Chin

Allison Connolly

Jeffrey Charles Hawkins

William Seaton

Nobuhiro Yanagisawa

Iyothsna Nagaraja

Gokul Subramanian

Venkatachalam Valliappan

Yuen Ting Cheng

Guan Sin Chok

Gene A Bornzin

Samuel D Naffziger

Michael Mantor

Edward Karst

John J Wuu

Skyler Jonathon Saleh

Chih-Wei Chen

Alan Dodson Smith

Fei Guo

Gabriel Wong

David Hugh McIntyre

Rajesh Raheja

Chia-Ken Leong

Rajanatha Shettigara

Michael S Alfano

Kong Toon Ng

Maurizio Paganini

Rajasekaran Swaminathan

Kaushik Mysore Srinivasa Setty

Ed Macosky

Satoru Kumashiro

Radhika Narang

Ryuichi Moriizumi

Sean P Collins

Deepak Vasant Kulkarni

Chintan Buch

Computer implemented systems and methods are disclosed for automatically clustering and canonically identifying related data in various data structures. Data structures may include a plurality of records, wherein each record is associated with a respective entity. In accordance with some embodiments, the systems and methods further comprise identifying clusters of records associated with a respective entity by grouping the records into pairs, analyzing the respective pairs to determine a probability that both members of the pair relate to a common entity, and identifying a cluster of overlapping pairs to generate a collection of records relating to a common entity. Clusters may further be analyzed to determine canonical names or other properties for the respective entities by analyzing record fields and identifying similarities.

Systems and methods for automatic clustering and canonical designation of related data in various data structures

Blood pump systems include a left ventricular assist device that is controlled to inhibit onset or worsening of right ventricular failure. A blood pump system includes a left ventricular assist device, a pulmonary artery pressure sensor, and a controller. The pulmonary artery pressure sensor is configured for generating a pressure signal indicative of a blood pressure in the pulmonary artery of the patient. The controller is configured to control operation of the left ventricular assist device, process the pressure signal to generate pulmonary artery pressure data indicative of right ventricular afterload of the patient, and adjust at least one operating parameter of the left ventricular assist device based on the pulmonary artery pressure data to reduce a deviation between the right ventricular afterload of the patient and a target right ventricular afterload for the patient.

Methods and systems for controlling a left ventricular assist device

Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.

Molded chip package with anchor structures

A semiconductor package for high-speed die connections using a conductive insert, the semiconductor package comprising: a die; a plurality of redistribution layers; a conductive insert housed in a perforation through the plurality of redistribution layers; and a conductive bump conductively coupled to an input/output (I/O) connection point of the die via the conductive insert.

High-speed die connections using a conductive insert

Various molded fan-out semiconductor chip devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer that has internal conductor structures, a redistribution layer (RDL) structure positioned on the first molding layer and electrically connected to the internal conductor structures, a semiconductor chip positioned on and electrically connected to the RDL structure, and a second molding layer positioned on the RDL structure and at least partially encapsulating the semiconductor chip.

Fan-out packages with warpage resistance

A semiconductor package includes a package substrate having a first surface and an opposing second surface, and further includes an integrated circuit (IC) die disposed at the second surface and having a third surface facing the second surface and an opposing fourth surface. The IC die has a first region comprising one or more metal layers and circuit components for one or more functions of the IC die and a second region offset from the first region in a direction parallel with the third and fourth surfaces. The semiconductor package further includes a voltage regulator disposed at the fourth surface in the second region and having an input configured to receive a supply voltage and an output configured to provide a regulated voltage, and also includes a conductive path coupling the output of the voltage regulator to a voltage input of circuitry of the IC die.

3D semiconductor package with die-mounted voltage regulator

A chip for hybrid bonded interconnect bridging for chiplet integration, the chip comprising: a first chiplet; a second chiplet; an interconnecting die coupled to the first chiplet and the second chiplet through a hybrid bond.

Hybrid bonded interconnect bridging

Apparatuses, systems and methods for efficiently generating a package substrate. A semiconductor fabrication process (or process) fabricates each of a first glass package substrate and a second glass package substrate with a redistribution layer on a single side of a respective glass wafer. The process flips the second glass package substrate upside down and connects the glass wafers of the first and second glass package substrates together using a wafer bonding technique. In some implementations, the process uses copper-based wafer bonding. The resulting bonding between the two glass wafers contains no air gap, no underfill, and no solder bumps. Afterward, the side of the first glass package substrate opposite the glass wafer is connected to at least one integrated circuit. Additionally, the side of the second glass package substrate opposite the glass wafer is connected to a component on the motherboard through pads on the motherboard.

Glass core package substrates

Systems and methods are described for automatically processing data stored in one or more databases using machine learning to detect entities (such as health care providers, health care plan members, patients, pharmacies, and so forth) associated with health care claims that are suspected of fraudulent, wasteful, and/or abusive activity. The techniques may further or alternatively involve generating and presenting, for a set of suspected entities, natural language explanatory information explaining how and/or why each of the respective suspected entities is considered to be suspected of fraudulent, wasteful, and/or abusive activity. Feedback provided by fraud analysts and/or other subject matter experts in the misuse detection space is used to facilitate misuse detection and misuse detection presentation.

Fraud lead detection system for efficiently processing database-stored data and automatically generating natural language explanatory information of system results for display in interactive user interfaces

A semiconductor device includes a first die, the first die including a first dielectric layer and a plurality of first bond pads formed within apertures in the first dielectric layer, and a second die bonded to the first die, the second die including a second dielectric layer and a plurality of second bond pads protruding from the second dielectric layer. The first die is bonded to the second die such that the plurality of second bond pads protrude into the apertures in the first dielectric layer to establish respective metallurgical bonds with the plurality of first bond pads. A reduction in the distance between the respective bond pads of the dies results in a lower temperature for establishing a hybrid bond.

Low temperature hybrid bonding

A model management system provides a centralized repository for storing and accessing models. The model management system receives an input to store a model object in a first model state generated based on a first set of known variables. The model management system generates a first file including a first set of functions defining the first model state and associates the first file with a model key identifying the model object. The model management system receives an input to store the model object in a second model state having been generated based on the first model state and a second set of known variables. The model management system generates a second file including a second set of functions defining the second model state and associates the second file with the model key. The model management system identifies available versions of the model object based on the model key.

Model object management and storage system

A three-dimensional integrated circuit includes a first die structure having a first geometry. The first die structure includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The three-dimensional integrated circuit includes a second die structure having a second geometry. A stacked portion of the second die structure is aligned with the first region. The three-dimensional integrated circuit includes an additional die structure stacked with the first die structure and the second die structure. The additional die structure has the first geometry or the second geometry.

Offset-aligned three-dimensional integrated circuit

A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via a passive crosslink. The passive crosslink is a passive interposer die dedicated for inter-chiplet communications and partitions systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.

GPU chiplets using high bandwidth crosslinks

Various circuit boards with mounted passive components and method of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes at least partially encapsulating a first plurality of passive components in a molding material to create a first molded passive component group. The first molded passive component group is mounted on a surface of a circuit board. The first plurality of passive components are electrically connected to the circuit board.

Circuit board with compact passive component arrangement

Growing community of inventors

Saratoga, CA, United States of America

Rahul Kumar Agarwal