Advanced Micro Devices Corporation

Ati Technologies Ulc

Rahul Agarwal

Gabriel H Loh

Brett P Wilkerson

Raja Swaminathan

Milind S Bhagavat

Chia-Hao Cheng

Kong Toon Ng

Skyler Jonathon Saleh

Ruijin Wu

Fei Guo

Priyal Shah

Arsalan Alam

An embodiment of a semiconductor chip device can include a molding layer having a first side and a second side, an interconnect chip at least partially encased in the molding layer, the interconnect chip comprising a through substrate via (TSV) that extends through the interconnect chip, an insulating layer positioned on the first side of the molding layer, and a conductive structure that is positioned vertically below the interconnect chip and extends through the insulating layer, wherein the conductive structure is electrically coupled to the TSV.

Semiconductor chip device

Various molded semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a routing substrate and a semiconductor chip mounted on and electrically connected to the routing substrate. The semiconductor chip has plural side surfaces. A molding layer at least partially encases the semiconductor chip. The molding layer has a tread and a riser, the riser abutting at least some of the side surfaces.

Molded semiconductor chip package with stair-step molding layer

In an implementation, a semiconductor chip device includes a first semiconductor chip that includes a first portion and a second portion. The first portion can be a higher heat producing portion and the second portion can be a lower heat producing portion. A second semiconductor chip is stacked on the first semiconductor chip over the second portion. A dummy component is stacked on the first semiconductor chip over the first portion. The dummy component includes a plurality of thermal pipes providing a thermal path from a first surface of the dummy component to an opposite second surface of the dummy component.

Semiconductor chip device integrating thermal pipes in three-dimensional packaging

A semiconductor device includes a power delivery device die stack including a plurality of vertically arranged power delivery device dies. The plurality of power delivery device dies including at least a first power delivery device die and a second power delivery device die electrically connected to the first power delivery device die. The semiconductor device includes at least one external interconnect for providing a power input to the power delivery device die stack and at least one external interconnect for supplying a power output from the power delivery device die stack.

Stacking power delivery device dies

A semiconductor package includes a first mold layer at least partially encasing at least one photonic integrated circuit. A redistribution layer structure is fabricated on the first mold layer, the redistribution layer structure including dielectric material and conductive structures. A second mold layer at least partially encasing at least one semiconductor chip is fabricated on the redistribution layer structure. The redistribution layer structure provides electrical pathways between the at least one semiconductor chip and the at least one photonic integrated circuit. One or more voids are defined in the second mold layer in an area above an optical interface of the at least one photonic integrated circuit such that light is transmittable through dielectric material above the optical interface.

Fanout module integrating a photonic integrated circuit

A semiconductor module includes two or more semiconductor dies and an interconnect structure coupled to the two or more semiconductor dies. The interconnect structure implements a plurality of die-to-die connection pathways having a first density and a plurality of fan-out redistribution pathways having a second density that is different from the first density.

Mixed density interconnect architectures using hybrid fan-out

Various multi-die arrangements and methods of manufacturing the same are disclosed. In some embodiments, a method of manufacture includes a face-to-face process in which a first GPU chiplet and a second GPU chiplet are bonded to a temporary carrier wafer. A face surface of an active bridge chiplet is bonded to a face surface of the first and second GPU chiplets before mounting the GPU chiplets to a carrier substrate. In other embodiments, a method of manufacture includes a face-to-back process in which a face surface of an active bridge chiplet is bonded to a back surface of the first and second GPU chiplets.

Growing community of inventors

Santa Clara, CA, United States of America

Rahul Agarwal