Qualcomm Incorporated

Raheel Khan

Steve Hengchen Hsu

Fahad Ali Mujahid

Afshin Shiravi

Scott Cheng

Joaquin Romera

Gayatri Singaravelu

Graig Zethner

Pascal Philippe

Joseph C Chan

Naveed U Zaman

Ron Shalev

Vijay Bantval

Hung-Chih Lai

Scott Wang-Yip Cheng

Dong Wook Seo

Kanwal Banga

Vaidyanathan Seetharaman

Kanwal Preet S Banga

Jun Ho Bahn

Srinivas Badam

Samuel Sangmin Rhee

Transmission of data over a serial link based on a unidirectional clock signal is provided. A unidirectional clock signal is generated based on a first clock of a master device. The unidirectional clock signal is sent to a slave device that is connected to the serial link. The master device transmits data to the slave device over the serial link based on the first clock. The slave device receives the unidirectional clock signal from a master device. The slave device transmits data over the serial link to the master device based on the unidirectional clock signal.

Unidirectional clock signaling in a high-speed serial link

Systems, methods, and apparatus for synchronizing timing in devices coupled to a data communication link are disclosed. In one example, a first device programs a future system time value in a second device. The first device launches a low-latency trigger signal that causes the future system time value to be loaded into a timer of the second device when a timer of the first device matches the future system time value. The second device measures phase difference between the trigger signal and edges of a clock signal used for timing in the second device. The phase difference is measured using an oversampling clock that provides a desired measurement reliability. The measured phase difference permits the first device to accurately determine system time as applied to the second device. The trigger signal can be provided on existing pins used by first and second devices in accordance with communication protocols and specifications.

Low-latency low-uncertainty timer synchronization mechanism across multiple devices

Systems and methods for performing on-the-fly format conversion on data vectors during load/store operations are described herein. In one embodiment, a method for loading a data vector from a memory into a vector unit comprises reading a plurality of samples from the memory, wherein the plurality of samples are packed in the memory. The method also comprises unpacking the samples to obtain a plurality of unpacked samples, performing format conversion on the unpacked samples in parallel, and sending at least a portion of the format-converted samples to the vector unit.

On-the-fly conversion during load/store operations in a vector processor

Various aspects describe an on-chip, hardware error-generator component. In some cases, the hardware error-generator component connects to a data path between two components contained within a same chip. Upon receiving an error simulation input, the hardware error-generator component modifies data being transmitted on the data path by inserting a data pattern that simulates an error condition. Alternately or additionally, the hardware error-generator randomly alters one or more of the transmitted data bits.

Self-error injection technique for point-to-point interconnect to increase test coverage

A serial transceiver that includes programmable distributed data processing is provided. The serial transceiver can include an ingress channel that receives serial ingress data and an egress channel that transmits serial egress data. The serial transceiver can also include first and second layers that are one and another of a transport layer, a link layer, or a physical layer (PHY). The first and second layers can include elements that process the ingress data and the egress data. The serial transceiver can also include a programmable controller, a first interconnect that connects the programmable controller to the first layer, and a second interconnect that connects the programmable controller to the second layer. The programmable controller can send first data via the first interconnect to the first layer, and the first data can be processed by one of the first layer elements.

Programmable distributed data processing in a serial link

Vector processing engines (VPEs) employing reordering circuitry in data flow paths between execution units and vector data memory to provide in-flight reordering of output vector data stored to vector data memory are disclosed. Related vector processor systems and methods are also disclosed. Reordering circuitry is provided in data flow paths between execution units and vector data memory in the VPE. The reordering circuitry is configured to reorder output vector data sample sets from execution units as a result of performing vector processing operations in-flight while the output vector data sample sets are being provided over the data flow paths from the execution units to the vector data memory to be stored. In this manner, the output vector data sample sets are stored in the reordered format in the vector data memory without requiring additional post-processing steps, which may delay subsequent vector processing operations to be performed in the execution units.

Vector processing engines (VPEs) employing reordering circuitry in data flow paths between execution units and vector data memory to provide in-flight reordering of output vector data stored to vector data memory, and related vector processor systems and methods

Vector processing engines (VPEs) employing format conversion circuitry in data flow paths between vector data memory and execution units to provide in-flight format-converting of input vector data to execution units for vector processing operations are disclosed. Related vector processor systems and methods are also disclosed. Format conversion circuitry is provided in data flow paths between vector data memory and execution units in the VPE. The format conversion circuitry is configured to convert input vector data sample sets fetched from vector data memory in-flight while the input vector data sample sets are being provided over the data flow paths to the execution units to be processed. In this manner, format conversion of the input vector data sample sets does not require pre-processing, storage, and re-fetching from vector data memory, thereby reducing power consumption and not limiting efficiency of the data flow paths by format conversion pre-processing delays.

Vector processing engines (VPEs) employing format conversion circuitry in data flow paths between vector data memory and execution units to provide in-flight format-converting of input vector data to execution units for vector processing operations, and related vector processor systems and methods

Vector processing engines (VPEs) employing a tapped-delay line(s) for providing precision filter vector processing operations with reduced sample re-fetching and power consumption are disclosed. Related vector processor systems and methods are also disclosed. The VPEs are configured to provide filter vector processing operations. To minimize re-fetching of input vector data samples from memory to reduce power consumption, a tapped-delay line(s) is included in the data flow paths between a vector data file and execution units in the VPE. The tapped-delay line(s) is configured to receive and provide input vector data sample sets to execution units for performing filter vector processing operations. The tapped-delay line(s) is also configured to shift the input vector data sample set for filter delay taps and provide the shifted input vector data sample set to execution units, so the shifted input vector data sample set does not have to be re-fetched during filter vector processing operations.

Vector processing engines (VPEs) employing a tapped-delay line(s) for providing precision filter vector processing operations with reduced sample re-fetching and power consumption, and related vector processor systems and methods

Vector processing engines (VPEs) employing merging circuitry in data flow paths between execution units and vector data memory to provide in-flight merging of output vector data stored to vector data memory are disclosed. Related vector processing instructions, systems, and methods are also disclosed. Merging circuitry is provided in data flow paths between execution units and vector data memory in the VPE. The merging circuitry is configured to merge an output vector data sample set from execution units as a result of performing vector processing operations in-flight while the output vector data sample set is being provided over the output data flow paths from the execution units to the vector data memory to be stored. The merged output vector data sample set is stored in a merged form in the vector data memory without requiring additional post-processing steps, which may delay subsequent vector processing operations to be performed in execution units.

Vector processing engines (VPEs) employing merging circuitry in data flow paths between execution units and vector data memory to provide in-flight merging of output vector data stored to vector data memory, and related vector processing instructions, systems, and methods

Vector processing engines (VPEs) employing a tapped-delay line(s) for providing precision correlation/covariance vector processing operations with reduced sample re-fetching and/or power consumption are disclosed. The VPEs disclosed herein are configured to provide correlation/covariance vector processing operations, such as code division multiple access (CDMA) correlation/covariance vector processing operations as a non-limiting example. A tapped-delay line(s) is included in the data flow paths between memory and execution units in the VPE. The tapped-delay line (s) is configured to receive and provide an input vector data sample set to execution units for performing correlation/covariance vector processing operations. The tapped-delay line(s) is also configured to shift the input vector data sample set for each filter delay tap and provide the shifted input vector data sample set to the execution units, so the shifted input vector data sample set need not be re-fetched from the vector data file during the filter vector processing operations.

Vector processing engines (VPEs) employing tapped-delay line(s) for providing precision correlation / covariance vector processing operations with reduced sample re-fetching and power consumption, and related vector processor systems and methods

Embodiments disclosed herein include vector processing engines (VPEs) having programmable data path configurations for providing multi-mode vector processing. Related vector processors, systems, and methods are also disclosed. The VPEs include a vector processing stage(s) configured to process vector data according to a vector instruction executed in the vector processing stage. Each vector processing stage includes vector processing blocks each configured to process vector data based on the vector instruction being executed. The vector processing blocks are capable of providing different vector operations for different types of vector instructions based on data path configurations. Data paths of the vector processing blocks are programmable to be reprogrammable to process vector data differently according to the particular vector instruction being executed. In this manner, a VPE can be provided with its data paths configuration programmable to execute different types of functions based on data path configuration according to the vector instruction being executed.

Vector processing engines having programmable data path configurations for providing multi-mode vector processing, and related vector processors, systems, and methods

Systems and method for reading data samples in reverse group order are described herein according to various embodiments of the present disclosure. In one embodiment, a method for reading data samples in a memory is provided, wherein the data samples correspond to an operand of a vector operation, the data samples are grouped into a plurality of different groups, and the different groups are spaced apart by a plurality of addresses in the memory. The method comprises reading the groups of data samples in reverse group order, and, for each group, reading the data samples in the group in forward order.

Sample process ordering for DFT operations

Systems and methods for despreading a received signal are described herein. In one embodiment, a vector processor comprises a plurality of code generators, wherein each code generator is configured to generate a different code corresponding to a different code hypothesis. The vector processor also comprises a plurality of despread blocks coupled to a common input for receiving samples of a signal, wherein each despread block is configured to despread at least a portion of the samples with a different one of the codes to generate respective despreaded samples and to accumulate the respective despreaded samples over a length of the code.

Low-power circuit and implementation for despreading on a configurable processor datapath

Systems and methods for performing a rake-finger operation on a vector processor are described herein. In one embodiment, a method for rake-finger processing comprises loading samples from a register into an execution unit, performing a rake-finger operation on the samples in the execution unit, and writing results from the rake-finger operation to the register. Performing the rake-finger operation comprises performing a finite impulse response (FIR) filter operation, and performing a despread operation, wherein filtered samples from the FIR filter operation are input to the despread operation without going through the register.

Instruction and method for fused rake-finger operation on a vector processor

Vector processing engines (VPEs) having programmable data path configurations for providing multi-mode Radix-2butterfly vector processing circuits. Related vector processors, systems, and methods are also disclosed. The VPEs disclosed herein include a plurality of vector processing stages each having vector processing blocks that have programmable data path configurations for performing Radix-2butterfly vector operations to perform Fast Fourier Transform (FFT) vector processing operations efficiently. The data path configurations of the vector processing blocks can be programmed to provide different types of Radix-2butterfly vector operations as well as other arithmetic logic vector operations. As a result, fewer VPEs can provide desired Radix-2butterfly vector operations and other types arithmetic logic vector operations in a vector processor, thus saving area in the vector processor while still retaining vector processing advantages of fewer register writes and faster vector instruction execution times over scalar processing engines.

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Tustin, CA, United States of America

Raheel Khan