Sambanova Systems, Inc.

Raghu Prabhakar

Ram Sivaramakrishnan

Sumti Jairath

Gregory Frederick Grohoski

Manish K Shah

Matheen Musaddiq

Kin Hing Leung

David Brian Jackson

Arvind Krishna Sujeeth

Pramod Nataraja

Ruddhi Arun Chaphekar

Junjue Wang

Tejas Nagendra Babu Nama

Kaizhao Liang

Adi Fuchs

Mark Luttrell

Sitanshu Gupta

Ravinder Kumar

Ranen Chatterjee

Dawei Huang

Arnav Goel

David Alan Koeplinger

Martin Russell Raumann

Bandish B Shah

Emre Ali Burhan

Manoj Unnikrishnan

Nathan Francis Sheeley

Matthew Thomas Grimm

Ajit Punj

Sathish Terakanambi Sheshadri

Scott Layson Burson

Weiwei Chen

Yuan Lin

Luca Boasso

Matthew Vilim

Yaqi Zhang

Jinuk Shin

Andrew Deng

Youngmoon Choi

Yue Fu

Joshua Brot

Darshan Gandhi

Mingran Wang

Matthew Feldman

Maulik Desai

Subhra Mazumdar

Amitabh Menon

Darshan Dhimantkumar Gandhi

Likun Hao

Zhekun Zhang

Ayesha Siddiqua

Apurv Vivek

Abhishek Srivastava

Sankar Rachuru

Tram Tran

James Decker

Matt Feldman

Ruddhi Chaphekar

A statically reconfigurable dataflow architecture processor (SRDAP) performs an N-dimensional affine transform specified by a matrix on an input image to produce an output image includes L address pattern memory units (PMUs) comprising a memory arranged as a vector of L banks, and L corresponding data PMUs. Each data PMU receives a copy of the input image. In parallel: each address PMU writes an L-vector of addresses of input pixels to the vector of L banks and reads a single address of the written L-vector of addresses from a predetermined bank corresponding to a PMU number of the address PMU among the L address PMUs, and each data PMU receives the single address from the corresponding address PMU and uses it to read a single input pixel from the data PMU memory. A tree of pattern compute units coalesces the L single input pixels into an L-vector of input pixels.

Dataflow architecture processor statically reconfigurable to perform N-dimensional affine transformation in parallel manner by replicating copies of input image across multiple scratchpad memories

A statically reconfigurable dataflow architecture processor (SRDAP) performs an N-dimensional affine transform specified by a matrix on an input image to produce an output image includes pattern compute units (PCUs) and pattern memory units (PMUs) interconnected by switches. PCUs have vector pipelines of functional units that perform operations on operands received from previous pipeline stages, another PCU, and/or PMUs. PMUs have memories loadable with the input image. The PCUs and PMUs are statically reconfigurable to, for all the output pixels: apply the matrix to vectors of output pixel coordinates to calculate corresponding vectors of input pixel coordinates, flatten the vectors of input pixel coordinates into vectors of PMU addresses of the input pixels, read values of the input pixels from the PMUs at the calculated input pixel addresses, and write vectors of the input pixel values to PMUs to form the output image.

Dataflow architecture processor statically reconfigurable to perform n-dimensional affine transformation

A system includes a coarse-grained reconfigurable (CGR) processor and a compiler configured to generate one or more configuration files for an application for execution on the CGR processor including an array of pattern compute units (PCUs) and pattern memory units (PMUs). A PCU is configured to perform an operation. A PMU comprises a plurality of data structures including a plurality of portions of operation-specific data related to the operation. The PMU is coupled to the PCU via a multi-segment datapath pipeline. The CGR processor is coupled to configure a segment of the datapath pipeline using a set of configurations bits corresponding to a portion of the operation-specific data related to the operation to activate to the segment, to further communicate the operation-specific data to the PCU via the activated segment. The CGR processor is coupled to switch among multiple PMU contexts in various segments sequentially to concurrently.

Multiple contexts for a memory unit in a reconfigurable data processor

A system with a cost estimation tool for estimating a realized bandwidth consumption of a logical edge between a logical producer unit and a logical consumer unit of an operation unit graph during placement and routing of the logical producer unit, the logical consumer unit, and the logical edge onto a reconfigurable processor is presented as well as a method of operating such a cost estimation tool and a non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to operate such a cost estimation tool The cost estimation tool may be configured to determine the realized bandwidth consumption of the tentative assignment based on an upper bandwidth limit of the logical edge, an end-to-end bandwidth, a scaling factor of a realized bandwidth, and a congestion estimation of the physical link.

Operating a cost estimation tool for placing and routing an operation unit graph on a reconfigurable processor

An integrated circuit (IC) includes an array of statically reconfigurable compute units for separation into mutually exclusive groups. Each group includes statically reconfigurable number of compute units. Each compute unit includes a register statically reconfigurable with a group identifier that identifies which group the compute unit belongs to, a counter statically reconfigurable to synchronously increment with the counters of all the other compute units such that all the counters have the same value each clock cycle, and control circuitry that prevents the compute unit from starting to process data until the counter value matches the identifier. According to operation of the register, the counter, and the control circuitry, no more than the statically reconfigurable number of the compute units are allowed to start processing data concurrently to mitigate supply voltage droop caused by a time rate of change of current drawn by the IC through inductive loads of the IC.

Integrated circuit that mitigates inductive-induced voltage droop using compute unit group identifiers

The technology disclosed provides a system that comprises a processor with computing units on an integrated circuit substrate. The processor is configured to map a program across multiple hardware stages with each hardware stage executing a corresponding operation of the program at a different stage latency dependent on an operation type and an operand format. The system further comprises a runtime logic that configures the compute units with configuration data. The configuration data causes first and second producer hardware stages in a given compute unit to execute first and second data processing operations and produce first and second outputs at first and second stage latencies, and synchronizes consumption of the first and second outputs by a consumer hardware stage in the given compute unit for execution of a third data processing operation by introducing a register storage delay that compensates for a difference between the first and second stage latencies.

Compiler-based input synchronization for processor with variant stage latencies

A cost estimation tool in a system for implementing an operation unit graph on a reconfigurable processor is presented as well as a method of operating a cost estimation tool for determining scaled logical edge bandwidths in an operation unit graph in preparation of placing and routing the operation unit graph onto a reconfigurable processor. The cost estimation tool may be configured to receive the operation unit graph, divide the operation unit graph in first and second subgraphs, determine maximum latencies of the first and second subgraphs, and determine a scaled logical edge bandwidth of a logical edge that couples a first logical unit of M logical units in the first subgraph with a second logical unit of N logical units in the first subgraph based on M, N, and scaled bandwidth limits of the M and N logical units.

Estimating a scaled cost of implementing an operation unit graph on a reconfigurable processor

A data processing system includes memory and reconfigurable processors, operatively coupled to the memory, configured to execute a sequence of subgraphs of a graph. The sequence of subgraphs includes a preceding subgraph and a succeeding subgraph. The data processing system also includes data flow logic, operatively coupled to the reconfigurable processors and the memory, configured to store a tiled output of the preceding subgraph as a composed input in the memory and make available parts of the composed input for processing by the succeeding subgraph.

Lossless tiling in convolution networks—data flow logic

A data processing system includes a coarse-grained reconfigurable (CGR) processor and a compiler configured to generate one or more configuration files for an application for execution on the CGR processor. The CGR processor includes an array of pattern compute units (PCUs) and pattern memory units (PMUs). A PCU comprises a plurality of single-instruction multiple data (SIMD) units configurable to form a datapath. The CGR processor is coupled to configure a datapath including a SIMD, using a set of configurations bits corresponding to an operation related to the task. The CGR processor is coupled to switch among the plurality of tasks and their corresponding PCU contexts during execution of the dataflow graph. The CGR processor is coupled to switch among tasks via static switching or dynamic switching, in response to the triggering of a task complete event generated by a preset counter, indicating completion of a current task.

Multiple contexts for a compute unit in a reconfigurable data processor

A method includes analyzing a dataflow graph to generate configuration information loadable into an integrated circuit. The dataflow graph specifies operations to be performed and data dependencies between the operations. The configuration information is usable by the integrated circuit to configure compute units of the integrated circuit to perform respective one or more of the operations of the dataflow graph, control data flow between the compute units to accomplish the data dependencies between the respective operations performed by the compute units, and control when each compute unit starts to perform the respective operations on the data to mitigate supply voltage droop caused by a time rate of change of current drawn by the integrated circuit through inductive loads of the integrated circuit.

Compiler that generates configuration information for configuring an integrated circuit to mitigate inductive-induced voltage droop

A reconfigurable processing unit is disclosed, comprising a first internal network and a second internal network with different protocols, an interface to an external network with a different protocol, a first configurable unit connected to the first internal network, a second configurable unit connected to both the first internal network and the second internal network, and a third configurable unit connected to both the second internal network and the interface to the external network. The third configurable unit is configured to receive a payload from the external network and send the transaction type identifier and the source application ID to the second configurable unit over the second internal network. The second configurable unit sends information to the first configurable unit based on the transaction type identifier and the source application ID matching the local application ID retrieved from the register.

Reconfigurable dataflow unit with streaming write functionality

A reconfigurable data processor comprises an array of configurable units and a bus system. The bus system is connected to the array of configurable units. The bus system includes a top level network and an array level network. The top level network is connected to an external data interface for communication with memory outside of the array of configurable units. The array level network is connected to configurable units in the array of configurable units.

Top level network and array level network for reconfigurable data processors

A tile of an embodiment of a coarse-grain reconfigurable architecture (CGRA) is based on an array of fused compute-memory units (FCMUs), pattern memory units (PMUs), and/or pattern compute units (PCUs) arranged in two dimensions, M×N. Unless clearly noted from context, any reference to a FCMU, PCU, or PMU may refer to one or more of the other units. The communication between a set of FCMUs is performed over a (M+1)×(N+1) switch fabric called the array-level network (ALN) where each switch has connections to its neighboring FCMUs and to neighboring switches in each of the four directions.

Dynamic destination id in an array level network of a reconfigurable dataflow processor

The technology disclosed relates to storing a dataflow graph with a plurality of compute nodes that transmit data along data connections, and controlling data transmission between compute nodes in the plurality of compute nodes along the data connections by using control connections to control writing of data.

Flow control for reconfigurable processors

A data processing system receives a graph that includes a sequence of layers and executes graph cuts between a preceding layer in the graph and a succeeding layer in the graph that succeeds the preceding layer. The preceding layer generates a set of tiles on a tile-by-tile basis and the succeeding layer processes a tensor that includes multiple tiles in the set of tiles. Thus the graph is partitioned into a sequence of subgraphs, and a subgraph in the sequence of subgraphs including a sub-sequence of layers in the sequence of layers. One or more configuration files is generated to configure runtime logic to execute the sequence of subgraphs and the one or more configuration files are stored on a computer-readable media.

Lossless tiling in convolution networks—section cuts

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San Jose, CA, United States of America

Raghu Prabhakar