Advanced Micro Devices Corporation

Vantis Corporation

Redfern Integrated Optics, Inc.

Radu M Barsan

Sunil D Mehta

Jonathan Lin

Xiao-yu Li

Bradley A Sharpe-Geisler

Jack Zezhong Peng

Lew Stolpner

The present invention relates to various methods of fabricating Planar Bragg Gratings (PBG) in a doped waveguide in a Planar Lightwave Circuit (PLC) device, suppressing unwanted parasitic grating effects during fabrication of the device. One approach to reduce parasitic gratings is to use a hard mask before the waveguide photolithography and etch, that results in a steeper sidewall angle that reduces or eliminates the parasitic grating effect. Another method of reducing parasitic grating effect is to deposit a layer of developable Bottom Anti Reflective Coating (BARC) prior to depositing the photo resist for waveguide etch. A third method of resisting parasitic gratings comprises using a planarizing undoped silica layer as a barrier layer on top of the core. During subsequent high temperature annealing germanium outdiffuses laterally into the cladding. The net effect is an optical waveguide with improved lateral uniformity because germanium diffusion smoothes out the sidewall roughness created during the waveguide reactive ion etch process. The undoped silica (SiO2) layer on top of the grating also serves the purpose of significantly reducing germanium outdiffusion from the core in the upward direction.

Device fabrication with planar bragg gratings suppressing parasitic effects

A nitride layer is deposited over a field oxide layer used to separate transistors formed in a substrate, the nitride layer serving to decrease transistor current leakage. The nitride layer has a dense lattice, effectively blocking H&plus; and Na&plus; penetration from overlying layers into the field oxide. Positive ions such as H&plus; and Na&plus; penetrating into the field oxide layer cause a p-substrate under the field oxide layer to become inverted or act like an n-type substrate, creating leakage current between source and drain regions of transistors which the field oxide layer separates. When high transistor threshold voltages such as 12 volts or more are desired, the nitride layer provides a significant reduction in current leakage.

Field leakage by using a thin layer of nitride deposited by chemical vapor deposition

This invention includes a semiconductor device having a gate formed on a semiconductor substrate with a low hydrogen content etch stop or barrier layer formed over the gate, and methods for manufacturing a semiconductor device with an etch stop or barrier layer with low free hydrogen content. The semiconductor device may have a hydrogen getter layer formed between the gate and the etch stop or barrier layer. The etch stop or barrier layer is a high temperature PECVD nitride film, a high temperature PECVD oxynitride film or a high temperature LPCVD nitride film. The hydrogen getter layer is P-doped film having a thickness between about 500 .ANG. and about 2000 .ANG. and is a PSG, BPSG, PTEOS deposited oxide film, or a BPTEOS deposited oxide film. The low free hydrogen content of the etch stop layer or barrier layer is achieved by a high temperature annealing step, performed at a higher temperature than the deposition temperature of the etch stop or barrier layer. Specific uses of the etch stop or barrier layers include manufacture of electrical contacts and local interconnects.

Annealing of silicon oxynitride and silicon nitride films to eliminate

A shallow trench isolation structure and a method for forming the same for use with non-volatile memory devices is provided so as to maintain sufficient data retention thereof. An epitaxial layer is formed on a top surface of a semiconductor substrate. A barrier oxide layer is formed on a top surface of the epitaxial layer. A nitride layer is deposited on a top surface of the barrier oxide layer. Trenches are formed through the epitaxial layer and the barrier oxide layer to a depth greater than 4000 .ANG. below the surface of the epitaxial layer so as to create isolation regions in order to electrically isolate active regions in the epitaxial layer. A liner oxide is formed on sidewalls and bottom of the trenches to a thickness between 750 .ANG. to 1500 .ANG.. As a result, leakage current in the sidewalls are prevented due to less thinning of the liner oxide layer by subsequent fabrication process steps.

Data retention of EEPROM cell with shallow trench isolation using

A decoder circuit formed on an integrated circuit substrate including at least one short channel depletion transistor having a low resistance path formed between the source and the drain regions. The low resistance path is provided by an implant into the channel region that forms a depletion channel wherein the channel region has a length less than a length of a channel region of transistors in the decoder circuit that handle input/output voltage levels for the decoder circuit.

Decoder circuit with short channel depletion transistors

An integrated circuit ('IC') having three different oxide layer thicknesses and a process for manufacturing the IC using a single oxide growth step is provided. A first region is formed on a substrate surface with oxidation enhancing properties. A second region is formed on the substrate surface with a dose of nitrogen that retards oxidation. An oxide layer is grown from the first and the second regions and a third region of the substrate such that the first, second, and third regions yield a first oxide layer for the capacitor, a second oxide layer for the read transistor and a third oxide layer for the write transistor.

Integrated circuit having, and process providing, different oxide layer

Controlling the thickness of borophosphorous tetraethyl orthosilicate (BPTEOS) used as all or part of the first inter-layer dielectric (ILD0) in manufacturing a semiconductor device containing an array of transistors to control the field leakage between transistors. Reducing field leakage enables the thickness of field oxide, typically used to reduce field leakage, to be reduced to increase device density in the transistor array.

Use of borophosphorous tetraethyl orthosilicate (BPTEOS) to improve

A method for improving the endurance and reliability of a floating gate transistor often used in memory applications by controlling the electric field induced across the tunnel oxide region of the floating gate when discharging electrons from the floating gate. The method comprises the steps of: allowing the active region to ground; and applying a program voltage to the floating gate over a period of time and at a magnitude, by increasing the voltage from zero volts to the magnitude over a first period of at least 1 millisecond (ms.), maintaining the voltage at the magnitude for a second period of around 10 ms.-100 ms. sufficient to place charge on the floating gate, and decreasing the voltage from the magnitude during a third period to zero volts in not greater than 50 microseconds.

Method of charging and discharging floating gage transistors to reduce

A process for forming CMOS transistors on a semiconductor substrate, wherein the plurality of transistors includes high-voltage N-channel and high-voltage P-channel transistors, and low-voltage N-channel and low-voltage P-channel transistors, wherein a tunnel oxide of a first thickness is required and a gate oxide of a second thickness is required is provided. The process comprises the steps of: forming a thick gate oxide on the surface of the substrate; forming a low voltage n-channel transistor mask, the mask including a plurality of windows exposing first portions of the thick gate oxide; implanting an n-type dopant into the substrate through said windows and through the thick gate oxide layer to form an n-dopant implant region; etching a first portion of the thick gate oxide exposing the surface of the substrate overlying the n-dopant implant region; stripping the low voltage n-channel mask; forming a low voltage p-channel transistor mask, the mask including a plurality of windows exposing the second portions of the thick gate oxide; implanting a p-type dopant into the substrate through said windows and through the thick gate oxide layer; etching a second portion of the thick gate oxide layer thereby exposing a first and second portions of the substrate surface; and simultaneously forming a tunnel oxide on the first exposed portion of the substrate and gate oxide on the second exposed portion of the substrate.

Simplified masking process for programmable logic device manufacture

An enhanced, scalable EEPROM memory cell is provided with a structure having a plurality of half-height tunnel oxide depletion mode transistors. The structure further has individual wordlines controlling the write and read transistors, respectively. With such a structure, lower voltages are used to program/erase the memory cell. The memory cell is scalable to small dimensions through the use of transistors having half-height tunnel oxide regions.

V.sub.pp only scalable EEPROM memory cell having transistors with thin

An improved method for screening a non-volatile memory device or programmable logic device including the steps of initially programming and then erasing a device for a predetermined number of cycles thereby providing a stressed device. Next, the stressed device is erased, providing an erased device. A first voltage value is measured across the floating gate of each cell of the erased device which is then stored for a predetermined period of time at a first predetermined temperature, providing a stored device. Next, the stored device is baked at a second predetermined temperature resulting in a baked device. Then, a second voltage value is measured across the floating gate of each cell of the baked device. Each of the first and the second voltage values are subtracted to provide a plurality of measured voltage drop values each of which are compared to an acceptable predetermined voltage drop value. The baked device is identified as defective and is discarded if any of the measured voltage drop values are greater than the acceptable predetermined voltage drop value. The first predetermined temperature is room temperature (i.e., 0.degree.-50.degree. C.), and the second predetermined temperature is greater than or equal to 250.degree. C.

Method for screening non-volatile memory and programmable logic devices

An integrated circuit device and manufacturing process wherein a first region is formed in a substrate with a dopant that enhances oxide formation and a second region is formed in the substrate with a dose of nitrogen that retards oxide formation. An oxide layer is grown over the first and the second regions and over a third region of the substrate such that the first, second, and third regions yield differing thicknesses of the oxide layer.

Method of forming multiple gate oxide thicknesses on a wafer substrate

An apparatus and method, the apparatus including an NMOS pass gate separating NMOS and PMOS transistors of a CMOS memory cell configured for tunneling during program and erase through the NMOS and PMOS transistors. The additional NMOS pass gate enables the CMOS memory cell to be utilized as a memory cell in a programmable logic device (PLD). The method includes steps for programming and erasing CMOS memory cells to prevent current leakage. The steps include applying specific voltages to the sources of the NMOS and PMOS transistors during program and erase, rather than leaving either source floating. Such voltages can be applied during program or erase without additional pass gates being connected to the sources of the PMOS or NMOS transistors of individual CMOS cells, or the additional pass gate provided between the drains of the PMOS and NMOS as in the described apparatus.

CMOS memory cell with tunneling during program and erase through the

An improved control gate-addressed CMOS memory cell is provided which allows for programming and erasing by tunneling through the gate oxides of the PMOS and NMOS transistors. The CMOS memory cell (400) includes a PMOS transistor (402), an NMOS transistor (403), and an NMOS pass transistor (405). A capacitor (430) has a first terminal coupled to a common floating gate (416) of the PMOS and NMOS transistors and has a second terminal coupled to a control gate node.

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Cupertino, CA, United States of America

Radu M Barsan