International Business Machines Corporation

Rachel Gordin

David Goren

Michael Zelikson

Edmund Juris Sprogis

Gary Dale Carpenter

Michael Jay Shapiro

Alan J Drake

Shlomo Shlafman

Roi Carmon

Amir Alon

Betty Livshitz

Stefano Sergio Oggioni

Thomas J Brunschwiler

Gerd Schlottig

Sue Ellen Strang

Kurt Alan Tallman

Youri V Tretiakov

Michele Castriotta

Anatoly Sherman

Sherman Anatoly

A chip package comprising: a chip stack comprising at least one chip; and a thermal power plane comprising at least two substantially parallel dielectric layers having conductive connectors patterned therein, the at least two dielectric layers electrically connected by vias, wherein said vias are substantially perpendicular to the at least two dielectric layers, wherein each of the vias electrically connects to a connector patterned within a dielectric layer of the at least two dielectric layers at a via connection, wherein an inductor used in supplying power to the at least one chip is formed from the vias and from connectors electrically connecting via connections on each of the at least two dielectric layers.

Integrated helical multi-layer inductor structures

A distributed active transformer is provided comprising a primary and a secondary winding. The primary winding comprises a first set of conductive vias extending in a direction between a first surface and a second surface of an element, a first set of first electrically conductive lines extending along the first surface, and a first set of second electrically conductive lines extending along the second surface. The secondary winding comprises a second set of conductive vias extending in a direction between the first surface and the second surface, a second set of first electrically conductive lines extending along the first surface, and a second set of second electrically conductive lines extending along the second surface. When energized, the primary winding generates magnetic flux extending in a direction parallel to the first surface and the second surface. The secondary winding receives energy transferred by the magnetic flux generated by the primary winding.

Stacked through-silicon via (TSV) transformer structure

A coil inductor and buck voltage regulator incorporating the coil inductor are provided which can be fabricated on a microelectronic element such as a semiconductor chip, or on an interconnection element such as a semiconductor, glass or ceramic interposer element. When energized, the coil inductor has magnetic flux extending in a direction parallel to first and second opposed surfaces of the microelectronic or interconnection element, and whose peak magnetic flux is disposed between the first and second surfaces. In one example, the coil inductor can be formed by first conductive lines extending along the first surface of the microelectronic or interconnection element, second conductive lines extending along the second surface of the microelectronic or interconnection element, and a plurality of conductive vias, e.g., through silicon vias, extending in direction of a thickness of the microelectronic or interconnection element. A method of making the coil inductor is also provided.

Coil inductor for on-chip or on-chip stack

A method for determining the layout of an interconnect line is provided including: providing a required width for the interconnect line; determining a layout of the interconnect line including slotting the interconnect line to provide two or more fingers extending along the interconnect line with an elongate slot separating adjacent fingers; and determining a number of elongate apertures to be arranged across the width of the interconnect line by comparing the required width with a maximal width for a solid metal feature, and a minimal elongate aperture width. The two or more fingers and elongate slot may be of constant width and equally spaced across the interconnect line width. The method may include selecting the number of fingers and the width of the slots to optimize the layout for a given layer technology.

Layout determining for wide wire on-chip interconnect lines

A system and method for design and modeling of vertical interconnects for 3DI applications. A design and modeling methodology of vertical interconnects for 3DI applications includes models that represent the frequency dependent behavior of vertical interconnects by means of multi-segment RLC scalable filter networks. The networks allow for accuracy versus computation efficiency tradeoffs, while maintaining correct asymptotic behavior at both high and low frequency limits. In the framework of the model it is shown that a major effect is pronounced frequency dependent silicon substrate induced dispersion and loss effects, which is considered in through silicon via (TSV) parallel Y-element parameters, including capacitance and conductance.

Method and system for design and modeling of vertical interconnects for 3DI applications

A tool for analog and mixed signal circuits includes a unit enabling a user to identify one or more critical interconnect lines in a chip architecture and one or more selectable, predefined topologies for said critical interconnect lines. Each topology includes one or more signal wires and a current return path. A majority of the electric field lines are contained within the boundary of the topology. The invention also includes a method for designing analog and mixed signal (AMS) integrated circuits (IC), including defining a chip architecture and a floor plan, identifying one or more critical interconnect lines and selecting pre-designed transmission line topologies for the critical interconnect lines.

Topologies and methodologies for AMS integrated circuit design

A method and system for design and modeling of transmission lines are provided. The method includes providing a set of models of core structures () of transmission line cells and expanding each of the models of core structures () to include different neighboring elements. The parameter characteristics of the expanded core structures (-) are compared to determine a model having a minimal sufficiently closed neighborhood environment. A closed neighborhood environment complies with design rules to ensure desired transmission line behavior in a real design environment. A model having a closed neighborhood environment can be used as a stand-alone model of the core structure describing the transmission line behavior in the actual design environment.

Method and system for design and modeling of transmission lines

A method of modeling capacitance for a structure comprising a pair of long conductors surrounded by a dielectric material and supported by a substrate. In particular, the structure may be on-chip coplanar transmission lines over a conductive substrate operated at very high frequencies, such that the substrate behaves as a perfect dielectric. It is assumed that the surrounding dielectric material is a first dielectric with a first permittivity (&#x2208;) and the substrate is a second dielectric with a second permittivity (&#x2208;). The method models the capacitance (C) for values of the first and second permittivity (&#x2208;, &#x2208;) based on known capacitance (C) computed for a basis structure with the same first permittivity (&#x2208;) and a different second permittivity (&#x2208;). Extrapolation or interpolation formulae are suggested to model the sought capacitance (C) through one or more known capacitances (C).

Capacitance modeling

A method of modeling capacitance for a structure comprising a pair of long conductors surrounded by a dielectric material and supported by a substrate. In particular, the structure may be on-chip coplanar transmission lines over a conductive substrate operated at very high frequencies, such that the substrate behaves as a perfect dielectric. It is assumed that the surrounding dielectric material is a first dielectric with a first permittivity (&#x3b5;) and the substrate is a second dielectric with a second permittivity (&#x3b5;). The method models the capacitance (C) for values of the first and second permittivity (&#x3b5;, &#x3b5;) based on known capacitance (C) computed for a basis structure with the same first permittivity (&#x3b5;) and a different second permittivity (&#x3b5;). Extrapolation or interpolation formulae are suggested to model the sought capacitance (C) through one or more known capacitances (C).

A method and system for design and modeling of transmission lines are provided. The method includes providing a set of models of core structures () of transmission line cells and expanding each of the models of core structures () to include different neighboring elements. The parameter characteristics of the expanded core structures (-) are compared to determine a model having a minimal sufficiently closed neighborhood environment. A closed neighborhood environment complies with design rules to ensure desired transmission line behaviour in a real design environment. A model having a closed neighborhood environment can be used as a stand-alone model of the core structure describing the transmission line behaviour in the actual design environment.

An integrated circuit design kit including one or more circuit components topologies, and one or more critical interconnect lines topologies. The interconnect line topologies may be predefined. The kit may further include one or more circuit components models and one or more critical interconnect lines models.

Interconnect-aware methodology for integrated circuit design

Methods, systems and apparatus for modeling capacitance for a structure comprising a pair of long conductors surrounded by a dielectric material and supported by a substrate. In particular, the structure may be on-chip coplanar transmission lines over a conductive substrate operated at very high frequencies, such that the substrate behaves as a perfect dielectric. It is assumed that the surrounding dielectric material is a first dielectric with a first permittivity (e) and the substrate is a second dielectric with a second permittivity (e). A method models the capacitance (C) for values of the first and second permittivity (e, e) based on known capacitance (C) computed for a basis structure with the same first permittivity (e) and a different second permittivity (e). Extrapolation or interpolation formulae are suggested to model the sought capacitance (C) through one or more known capacitances (C).

System and method of modelling capacitance of on-chip coplanar transmission line structures over a substrate

In a systemfor designing an integrated circuit, a preliminary design of the integrated circuit is defined and critical interconnect lines in the preliminary design are identified. Further, any critical interconnect lines which are affected by crossing lines in the preliminary design are identified, and a transmission line modelis defined to represent each critical interconnect line. A layout design of the integrated circuit, comprising circuit components and parameters thereof, is then defined using the preliminary design and the transmission line modelfor each critical interconnect line. Component parameters are then extracted from the layout design for simulation of the design using the extracted component parameters. During this design process, for each transmission line modelrepresenting a critical interconnect line affected by a crossing line, an environment terminalis provided. The environment terminalcomprises a connection to the modelvia at least one circuit component representing the effect of the crossing line on the model. The environment terminalis connected to the appropriate crossing line in the integrated circuit design, whereby crossing line effects are accommodated in the design process.

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Hadera, Israel

Rachel Gordin