Chartered Semiconductor Manufacturing Ltd (corporation)

Globalfoundries Singapore Pte. Ltd.

Qun Ying Lin

Sia Kim Tan

Soon Yoeng Tan

Huey Ming Chong

Liang Choo Hsia

Mei Sheng Zhou

Yang Pan

Zheng Zou

Gek Soon Chua

Ron-Fu Chu

Alex Kai Hung See

Wen Zhan Zhou

Hui Liu

Wenzhan Zhou

Martin Yeo

Hury Ming Chong

A method and a device are provided for diffracting incident light from a lithographic scanner in an IC process flow. Embodiments include forming a diffraction grating in a first layer on a semiconductor substrate; and forming a plurality of lithographic alignment marks in a second layer, overlying the first layer, wherein the diffraction grating has a width and a length greater than or equal to a width and length, respectively, of the plurality of lithographic alignment marks.

Litho scanner alignment signal improvement

A method for forming an integrated circuit (IC) is presented. The method includes providing a wafer having a substrate prepared with a photoresist layer. The photoresist layer is processed by passing a radiation from an exposure source of a lithography tool through a mask having a pattern. The process parameters of the lithography tool are determined by performing a pattern matching process. The photoresist layer is developed to transfer the pattern on the mask to the photoresist layer.

Determination of lithography tool process condition

A method of making a mask is disclosed. The method includes providing a first and a second mask layers and disposing a first phase shift region on the first mask layer. A second phase shift region is disposed on the second mask layer, wherein the first and second phase shift regions are out of phase. A continuous unit cell is formed in the first phase shift region. The unit cell comprises a center section and distinct extension sections. The extension sections are contiguous to and extend outwards from the center section. The distinct extension sections have a same width as the center section. The second phase shift region is adjacent to the unit cell in the first phase shift region.

Mask and method to pattern chromeless phase lithography contact hole

Apparatus is provided for determining presence of contamination on a lithography mask, including: a fluid trap having a base and at least one wall member extending substantially perpendicularly to the base for trapping fluid on a portion of the base when fluid introduced during a cleaning process of the mask is removed.

Monitoring structure

A chromeless phase shift mask and Method for making and using. The A chromeless phase shift mask is used to pattern contact holes. The chromeless phase shift mask preferably comprises: a first phase shift region and a second phase shift region; the first region is comprised of a unit cell which is comprised of a rectangular center section and at least three rectangular sections (legs) outwards extending from the rectangular center section. The second region is adjacent to said first region. The interference between the first and second phase shift regions creates a contact hole pattern.

A reticle structure and a method of forming a photoresist profile on a substrate using the reticle having a multi-level profile. The reticle comprises (1) a transparent substrate, (2) a partially transmitting 180 degree phase shift film overlying predetermined areas of the transparent substrate to transmit approximately 20 to 70% of incident light, and (3) an opaque film overlying the predetermined areas of the partially transmitting 180 degree phase shift film. The method comprises the following steps: a) depositing a photoresist film over the substrate; b) directing light to the photoresist film through the reticle, and c) developing the photoresist film to form an opening in the resist layer where light only passed thru the substrate, and to remove intermediate thickness of the photoresist film, in the areas where the light passed through the partially transmitting 180 degree phase shift film. In an aspect, the photoresist film is comprised of a lower photoresist layer and an upper photoresist layer. The lower photoresist layer is less sensitive to light than the upper photoresist layer. In an aspect, the resist profile is used to form a dual damascene shaped opening.

Method for dual damascene patterning with single exposure using tri-tone phase shift mask

A structure, a method of fabricating and a method of using a phase shift mask (PSM) having a first phase shifted section, a half tone section, and a second phase shifted section. The first phase shift section and the half tone section are shifted 180 degrees with the second phase shift region. Embodiments provide for (1) a half tone, single trench alternating phase shift mask and (2) a half tone, dual trench alternating phase shift mask. The half tone region provides advantages over conventional alternating phase shift masks.

Half tone alternating phase shift masks

A new method of avoiding resist notching in the formation of a polysilicon gate electrode in the fabrication of an integrated circuit device is described. Bare active areas are provided surrounded by field oxide isolation on a semiconductor substrate wherein the surface of the substrate has an uneven topography due to the uneven interface between the active areas and the isolation. A polysilicon layer is deposited over the active areas and the field oxide isolation of the substrate. The surface of the polysilicon layer is roughened using a plasma etching process wherein pits are formed on the surface which act as light traps. The roughened polysilicon layer is covered with a layer of photoresist. Portions of the photoresist layer are exposed to actinic light wherein reflection lights from the actinic light are trapped in the pits. The reflection lights do not reflect onto the unexposed portion of the photoresist layer. The photoresist layer is developed and patterned to form the desired photoresist mask for the polysilicon layer wherein the absence of reflection lights reflecting onto the unexposed portion of the photoresist results in the notch-free photoresist mask in the formation of a polysilicon gate electrode in the fabrication of an integrated circuit device.

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Singapore, Singapore

Qun Ying Lin