Globalfoundries Inc.

Qun Gao

Naved Ahmed Siddiqui

Ankur Arya

Hui Zang

Haiting Wang

Anthony I Chou

Haigou Huang

Brian Joseph Greene

John Ryan Sporre

Shesh Mani Pandey

Yi Qi

Yiheng Xu

Rishikesh Krishnan

Scott Beasor

Jerome Ciavatti

Jianwei Peng

Yanping Shen

Hsien-Ching Lo

Balaji Kannan

Xin Wang

Wei Hong

Chun Yu Wong

Bharat V Krishnan

Matthew W Stoker

Tek Po Rinus Lee

Yongjun Shi

Jae Gon Lee

Junsic Hong

Annie Levesque

Vishal Chhabra

Christopher Nassar

Curtis Durfee

Kyung Bum Koo

Stephen Furkay

A device including a triple-layer EPI stack including SiGe, Ge, and Si, respectively, with Ga confined therein, and method of production thereof. Embodiments include an EPI stack including a SiGe layer, a Ge layer, and a Si layer over a plurality of fins, the EPI stack positioned between and over a portion of sidewall spacers, wherein the Si layer is a top layer capping the Ge layer, and wherein the Ge layer is a middle layer capping the SiGe layer underneath; and a Ga layer in a portion of the Ge layer between the SiGe layer and the Si layer.

Device with highly active acceptor doping and method of production thereof

Integrated circuit devices include trenches in a material layer that divide the material layer into fins. With such devices, an insulator partially fills the trenches and contacts the material layer. The top surface of the insulator (e.g., the surface opposite where the insulator contacts the material layer) has a convex dome shape between at least two of the fins. The dome shape has a first thickness from (from the bottom of the trench) where the insulator contacts the fins, and a second thickness that is greater than the first thickness where the insulator is between the fins. Further, there is a maximum thickness difference between the first and second thicknesses at the midpoint between the fins (e.g., the highest point of the dome shape is at the midpoint between the fins). Also, the top surface of the first insulator has concave divots where the first insulator contacts the fins.

Fin reveal forming STI regions having convex shape between fins

A method of forming a gate structure with an undercut region includes, among other things, forming a plurality of fins above a substrate and an isolation structure above the substrate and between the plurality of fins, forming a placeholder gate structure above the plurality of fins in a first region and above the isolation structure in a second region, selectively removing a portion of the placeholder structure in the second region to define an undercut recess, forming a spacer structure adjacent the sacrificial gate structure, forming a dielectric layer adjacent the spacer structure and in the undercut recess, removing remaining portions of the placeholder gate structure to define a gate cavity, and forming a replacement gate structure in the gate cavity.

Method of forming gate structure with undercut region and resulting device

Methods form structures that include (among other components) semiconductor fins extending from a substrate, gate insulators contacting channel regions of the semiconductor fins, and gate conductors positioned adjacent the channel regions and contacting the gate insulators. Additionally, epitaxial source/drain material contacts the semiconductor fins on opposite sides of the channel regions, and source/drain conductive contacts contact the epitaxial source/drain material. Also, first insulating spacers are on the gate conductors. The gate conductors are linear conductors perpendicular to the semiconductor fins, and the first insulating spacers are on both sides of the gate conductors. Further, second insulating spacers are on the first insulating spacers; however, the second insulating spacers are only on the first insulating spacers in locations between where the gate conductors intersect the semiconductor fins.

Fin-type transistors with spacers on the gates

The manufacture of a FinFET device includes the formation of a composite sacrificial gate. The composite sacrificial gate includes a sacrificial gate layer such as a layer of amorphous silicon, and an etch selective layer such as a layer of silicon germanium. The etch selective layer, which underlies the sacrificial gate layer, enables the formation of a gate cut opening having a controlled critical dimension that extends through the composite sacrificial gate.

Composite sacrificial gate with etch selective layer

At least one method, apparatus and system providing semiconductor devices comprising a semiconductor substrate; a first fin and a second fin on the semiconductor substrate; a first epitaxial formation on the first fin and having an inner surface oriented toward the second fin and an outer surface oriented away from the second fin; a second epitaxial formation on the second fin and having an inner surface oriented toward the first fin and an outer surface oriented away from the first fin; and a conformal dielectric layer on at least portions of the inner and outer surfaces of the first epitaxial formation, on at least portions of the inner and outer surfaces of the first epitaxial formation and the second epitaxial formation, and merged between the inner surface of the first epitaxial formation and inner surface of the second epitaxial formation.

Methods, apparatus, and system for forming epitaxial formations with reduced risk of merging

The present disclosure is directed to various methods of diffusing contact extension dopants in a transistor device and the resulting devices. One illustrative method includes forming a first contact opening between two adjacent gate structures formed above a first fin, the first contact opening exposing a first region of the first fin, forming a first contact recess in the first region, forming a first doped liner in the first contact recess, performing an anneal process to diffuse dopants from the first doped liner into the first fin to form a first doped contact extension region in the first fin, and performing a first epitaxial growth process to form a first source/drain region in the first contact recess.

Diffused contact extension dopants in a transistor device

One illustrative method disclosed herein includes, among other things, forming a first fin having first and second opposing sidewalls and forming a first sidewall spacer positioned adjacent the first sidewall and a second sidewall spacer positioned adjacent the second sidewall, wherein the first sidewall spacer has a greater height than the second sidewall spacer. In this example, the method further includes forming epitaxial semiconductor material on the fin and above the first and second sidewall spacers.

Asymmetric formation of epi semiconductor material in source/drain regions of FinFET devices

One illustrative method disclosed herein includes, among other things, forming a conformal piezoelectric material liner layer on at least the opposing lateral sidewalls of a fin, forming a recessed layer of insulating material on opposite sides of the fin and on the conformal piezoelectric material liner layer, removing portions of the conformal piezoelectric material liner layer positioned above the recessed layer of insulating material to thereby expose a portion of the fin above the recessed upper surface, and forming a gate structure above the recessed layer of insulating material and around a portion of the fin positioned above the recessed upper surface.

Methods of making FinFET device comprising a piezoelectric liner for generating a surface charge

Device structures and fabrication methods for an on-chip resistor. A first Seebeck terminal is arranged to overlap with first and second resistor bodies of the on-chip resistor. A second Seebeck terminal is also arranged to overlap with the first and second resistor bodies. The second Seebeck terminal has a spaced relationship with the first Seebeck terminal along a length of the first and second resistor bodies. The temperature coefficient of resistance of the on-chip resistor is based at least in part on a Seebeck coefficient of first and second Seebeck terminals.

On-chip resistors with a tunable temperature coefficient of resistance

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Clifton Park, NY, United States of America

Qun Gao